Abstract: Logic circuitry formed in street areas between adjacent fabricated electronic devices may be used as auxiliary or redundant components to salvage one or more otherwise defective devices. Logic circuitry is selectively coupled to the defective device(s) to directly replace or facilitate the replacement of defective components on one or more fabricated devices, thereby resulting in a single operable electronic device. The invention may be used to increase the production yield of electronic devices, particularly, semiconductor integrated circuits. The invention permits the fabrication of discretionary wiring during the normal metalization of semiconductor layers to interconnect electronic devices at the same time as the formation of the normal wiring/circuitry of the devices.

Abstract: A method of fabricating a stack crown capacitor of a dynamic random access memory (DRAM) cell by using an oxynitride mask is disclosed. First, a dielectric layer and a silicon nitride layer are sequentially deposited over a substrate with an electrical device. Next, forming a contact in the silicon nitride layer and the dielectric layer, and depositing a first polysilicon layer to fill the contact. Next, depositing an oxide layer and an oxynitride layer sequentially, and then defining a bottom electrode pattern for etching the oxynitride layer and the oxide layer. Then, laterally etching the oxide layer, and depositing a second polysilicon layer. Next, etching the second polysilicon layer and the first polysilicon layer by using the oxynitride layer as a mask to form the bottom electrode. Next, removing the oxynitride layer, the oxide layer and partial silicon nitride layer. Finally, forming an interelectrode dielectric layer and a top electrode.

Abstract: A method of bonding a first substrate (10) to a second substrate (30) is described, comprising the steps of: coating an adhesive (28) onto a first major surface of said first substrate (10); aligning said first and second substrates (10, 30) so that said coated first major surface of said first substrate (10) is facing said second substrate (30) and is separated therefrom by a gap (47); deflecting at least one of said first and second substrates (10, 30) by exerting a pressure between said first and second substrates (10, 30) substantially at the center thereof so that the adhesive coating (28) substantially at the center of said first substrate (10) comes into contact with said second substrate (30); and allowing the remaining parts of said adhesive coated first major surface of said first substrate (10) to come into contact with said second substrate (30). Use of the method to produce composites, in particular transmissive liquid crystal display panels is also described.

Abstract: On a semiconductor substrate of P-type silicon, an active area including a channel forming region with a smaller dimension along the gate width and a source region and a drain region extending along the gate length is formed so as to be surrounded with an isolation area of an insulating oxide film. On the isolation area on the semiconductor substrate and the channel forming region of the active area, a gate electrode is formed with a gate insulating oxide film sandwiched therebetween. A channel lower insulating layer is formed, out of the same insulating oxide film for the isolation area, merely in an area below the channel forming region below the gate electrode in the active area of the semiconductor substrate.

Abstract: A method of forming a power integrated circuit device (100) including a semiconductor layer of first conductivity type. The semiconductor layer includes a front-side surface (103), a backside surface (116), and a scribe region (117). The semiconductor layer further including a plurality of active cells on the front-side surface (103). The present method includes forming a backside layer (116) of second conductivity type overlying the backside surface, and forming a continuous diffusion region (117) of the second conductivity type through the semiconductor layer to connect the scribe region to the backside layer (116).

Abstract: A method of manufacturing integrated circuits based on providing a test column of memory cells in the devices. Cells in the test column are selected by a portion of the addresses which identifies a row in the main array on the device. A test is executed to determine a characteristic of the device, and the results of that test are mapped to the portion of the address which identifies a row in the array. This produces a characteristic code address for the device which indicates the results of the test. Access to the test column on the device is enabled, and a bit is written in response to the characteristic code address in a memory cell on the test column. During manufacture the test column is read in order to classify the device according to the characteristic.

Abstract: The application of a dissimilar anti-reflective coating on a conductive layer during photolithographic processing is avoided, as by modifying a portion of the upper surface of the conductive layer to exhibit anti-reflective properties. In an embodiment of the present invention, impurity ions are implanted into a portion of the upper surface of an aluminum or an aluminum-alloy conductive layer to render the upper portion substantially amorphous and, hence, decrease its reflectivity to perform an anti-reflective function.

Abstract: An integrated curcuit includes a layered superlattice material having the .sub.formula A1w1.sup.+a1 A2.sub.w2.sup.+a2 . . . Aj.sub.wj.sup.+aj S1.sub.x1.sup.+s1 S2.sub.x2.sup.+s2 . . . Sk.sub.xk.sup.+sk B1.sub.y1.sup.+b1 B2.sub.y2.sup.+b2 . . . Bl.sub.yl.sup.+bl Q.sub.z.sup.-2, where A1, A2 . . . Aj represent A-site elements in a perovskite-like structure, S1, S2 . . . Sk represent superlattice generator elements, B1, B2 . . . Bl represent B-site elements in a perovskite-like structure, Q represents an anion, the superscripts indicate the valences of the respective elements, the subscripts indicate the number of atoms of the element in the unit cell, and at least w1 and y1 are non-zero. Some of these materials are extremely low fatigue ferroelectrics and are applied in non-volatile memories. Others are high dielectric constant materials that do not degrade or breakdown over long periods of use and are applied in volatile memories.

Abstract: A method of forming a DRAM capacitor that utilizes cap layers and spacers to surround the gate and bit line so that the necessary contact openings in a DRAM can be formed in two self-aligned contact processing operations. The capacitor of the DRAM is fabricated by forming contact node and openings within an insulating layer above a substrate, and then forming a first conductive layer conformal to the surface profile of the substrate above the substrate structure. Next, spacers are formed on the sidewalls of the conductive layer, and then a second conductive layer is formed filling the spacer between the spacers and over the substrate structure. Thereafter, a portion of the first conductive layer and the second conductive layer is removed to expose the spacers and the insulating layer. Finally, the spacers and the insulating layer are removed to expose a lower electrode structure that comprises the first and the second conductive layers.

Abstract: Apparatus and method for discharging the body of a monitored SOI device through first and second discharge circuits. The second discharge circuit is selectively activated when the body potential of the monitored SOI device is at a level such that the body charge of the monitored SOI device cannot be discharged entirely through the first discharge circuit within normal operating cycle time allowances.

Abstract: A high voltage DENMOS transistor (10) having improved ESD protection. The transistor (10) is optimized to provide maximum substrate current in order to turn on the inherent lateral npn transistor during an ESD event so that the lateral npn can dissipate the ESD event without damage to the transistor (10). This is accomplished by optimizing the overlap (A) of the drain extended region (16) and the gate electrode (28) to control the gate coupling to achieve maximum substrate current.

Abstract: A process for fabricating a DRAM metal capacitor structure, featuring simultaneous formation of specific bit line, and storage node features, has been developed. The DRAM capacitor storage node is comprised of a stack of tungsten interconnect structures, overlying specific insulator layers, connected by tungsten plugs, formed in the specific insulator layers. Removal of a portion of the upper level insulator layers, exposes a stack of tungsten plugs and tungsten interconnects, that comprise the metal storage node structure, for the DRAM metal capacitor structure. The process of fabricating the DRAM metal capacitor structure, features the simultaneous formation of a tungsten bit line contact plug, and a tungsten storage node contact plug, in addition to the simultaneous formation of a tungsten bit line interconnect structure, and a tungsten interconnect structure, used as components of the DRAM metal capacitor structure.

Abstract: A conductor film is deposited on a semiconductor substrate via an insulation film, and jogs formed on the surface of the conductor film immediately after the deposition are removed by using the chemical mechanical polishing method, the etch back method, or the like. And on the surface of the conductor film thus flattened, a mask member is formed of an inorganic insulation film such as a SOG film or a silicon oxide film deposited by using the chemical vapor deposition method. By dry etching using this mask member as the etching mask, the above described conductor film is processed to have a pattern of a semiconductor wiring layer or a capacitor electrode. As a result, fine processing of the conductor film having a columnar crystal structure is facilitated. In addition, it becomes possible to improve the precision of the electrode shape of the capacitor and implement a highly reliable capacitor.

Abstract: A transistor including an epitaxial layer with a first conductivity type, a base buried region with a second conductivity type, and a sinker base region with the second conductivity type which extends from a main surface of the transistor to the base buried region, and delimits, together with the base buried region, emitter fingers in the epitaxial layer. The transistor further includes an emitter buried region with the first conductivity type and a doping level which is higher than that of the epitaxial layer. The emitter buried region is embedded in the epitaxial layer in a position adjacent to the base buried region. A sinker emitter region having the first conductivity type and a doping level which is higher than that of the epitaxial layer and extends from the main surface to the emitter buried region inside the emitter fingers.

Abstract: An apparatus and method for the real-time, in-line testing of semiconductor wafers during the manufacturing process. In one embodiment the apparatus includes a probe assembly within a semiconductor wafer processing line. As each wafer passes adjacent the probe assembly, a source of modulated light, within the probe assembly, having a predetermined wavelength and frequency of modulation, impinges upon the wafer. A sensor in the probe assembly measures the surface photovoltage induced by the modulated light. A computer then uses the induced surface photovoltage to determine various electrical characteristics of the wafer.

Abstract: According to the present invention, a gate insulation film, a silicon film and silicon nitride film are laminated on a gate backing pad made of a gate metal film, and etching is carried out on the silicon nitride film such that it remains on the gate backing pad as a protective insulation film. Thus, the corrosion of the gate backing pad, which is caused as the etching solution penetrate the silicon film in defect, can be prevented. Further, a protective semiconductor layer formed by patterning the protective insulation film and the silicon film, is formed above the gate backing pad. Thus, the gate backing pad can be protected from the etching solution during the patterning of the pixel electrode made of ITO. Therefore, the disconnection of the gate backing pad can be prevented.

Abstract: Methods of forming integrated circuit capacitors having composite oxide-nitride-oxide (ONO) dielectric layers include the steps of forming a first electrically insulating layer on a semiconductor substrate and then forming a first conductive layer on the first electrically insulating layer. The first conductive layer and the first electrically insulating layer are then etched in sequence to define an opening in the first conductive layer which exposes upper and lower surfaces of the first conductive layer extending adjacent the opening. The exposed upper and lower surfaces of the first conductive layer are then cleaned to remove a native oxide film therefrom. A preferred composite dielectric layer is then formed on the first conductive layer. The composite dielectric layer comprises a first oxide layer which contacts the cleaned upper and lower surfaces of the first conductive layer, a nitride layer which contacts the first oxide layer and a second oxide layer which contacts the nitride layer.

Abstract: A plurality of semiconductor circuits provided on a semiconductor wafer are arranged in a plurality of rows. The plurality of semiconductor circuits of each row are connected in series through first and second conductive layers provided between adjacent two of the semiconductor circuits of each row. The plurality of semiconductor circuits are connected to power supply terminals provided on the semiconductor wafer. The first and second conductive layers may be provided separately from the higher and lower voltage side power supply lines, or one of the first and second conductive layers may be common to one of the higher and lower voltage side power supply lines. The power supply is connected to the power supply terminals and the plurality of semiconductor circuits is aged. After the aging, the power supply is disconnected from the power supply terminals.

Abstract: A method for fabricating custom integrated circuits includes the steps of 1) patterning the layer to be customized with a standard precision mask to define all possible connections, vias or cut-points, and 2) using a targeting energy beam to select the desired connections, vias or cut-points for customization.Consequently, the present invention requires no custom mask so that application specific integrated circuits (ASICs) can be produced with lower lead-time and costs when compared to prior methods.In other embodiments, a non-precision configuration mask may replace the targeting energy beam, where the configuration mask can be made by conventional mask-making techniques or by applying an opaque layer to a mask blank and using a targeting energy beam to selectively remove the desired portions of the opaque areas.

Abstract: An arrangement is provided for collecting, measuring and analyzing at least two specific wavelengths of optical emissions produced while etching a semiconductor wafer in a plasma chamber to determine an optimal endpoint for the etching process. The arrangement includes a sensor for gathering optical emissions, an interface for converting the intensity of optical emissions into corresponding electrical signals, and a controller for determining an optimal endpoint based on the corresponding electrical signals for the two specific wavelengths and other predetermined threshold data.