Patents Examined by Christopher D Birkhimer
  • Patent number: 11947452
    Abstract: A subset of blocks from a set of blocks of a memory device are identified based on a valid data count constraint. A first block from the subset of blocks is selected based on a valid data count of the first block. A second block from the subset of blocks is selected based on a data temperature of the second block. A comparison of the first block and the second block is performed in accordance with one or more comparison criterion. The first block or the second block is selected as a garbage collection source block based on the comparison. Garbage collection is performed at the garbage collection source block.
    Type: Grant
    Filed: June 1, 2022
    Date of Patent: April 2, 2024
    Assignee: Micron Technology, Inc.
    Inventors: Xiangyu Tang, David Ebsen, Ying Huang, Sundararajan Sankaranarayanan
  • Patent number: 11947810
    Abstract: A semiconductor memory device includes a memory cell array and a cyclic redundancy check (CRC) engine. The memory cell array includes a plurality of volatile memory cells coupled to respective ones of a plurality of word-lines and respective ones of a plurality of bit-lines. The CRC engine, during a memory operation on the memory cell array, detects an error in a main data and a system parity data provided from a memory controller external to the semiconductor memory device through a link, generates an error flag indicating whether the detected error corresponds to either a first type of error associated with the link or a second type of error associated with the volatile memory cells based on the system parity data and transmit the error flag to the memory controller.
    Type: Grant
    Filed: May 12, 2022
    Date of Patent: April 2, 2024
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Sungrae Kim, Hyeran Kim, Myungkyu Lee, Chisung Oh, Kijun Lee, Sunghye Cho, Sanguhn Cha
  • Patent number: 11941248
    Abstract: Approaches for data compression involve a compression circuit packing non-zero data elements of a succession of words of a plurality of blocks into packed words by packing non-zero data elements of one or more words of the succession in each packed word, and restricting each packed word to data elements of one uncompressed block. The compression circuit writes each packed word in a RAM and within a compressed address range associated with the uncompressed block when the packed word is full of non-zero data elements, or before the packed word is full if the next input word is of another uncompressed block.
    Type: Grant
    Filed: December 13, 2021
    Date of Patent: March 26, 2024
    Assignee: XILINX, INC.
    Inventors: Vamsi Krishna Nalluri, Sai Lalith Chaitanya Ambatipudi, Mrinal J. Sarmah, Rajeev Patwari, Shreyas Manjunath, Sandeep Jayant Sathe
  • Patent number: 11934656
    Abstract: Techniques are provided for implementing garbage collection and bin synchronization for a distributed storage architecture of worker nodes managing distributed storage composed of bins of blocks. As the distributed storage architecture scales out to accommodate more storage and worker nodes, garbage collection used to free unused blocks becomes unmanageable and slow. Accordingly garbage collection is improved by utilizing heuristics to dynamically speed up or down garbage collection and set sizes for subsets of a bin to process instead of the entire bin. This ensures that garbage collection does not use stale information about what blocks are in-use, and ensures garbage collection does not unduly impact client I/O processing or conversely falls behind on garbage collection. Garbage collection can be incorporated into a bin sync process to improve the efficiency of the bin sync process so that unused blocks are not needlessly copied by the bin sync process.
    Type: Grant
    Filed: April 11, 2022
    Date of Patent: March 19, 2024
    Assignee: NetApp, Inc.
    Inventors: Manan Dahyabhai Patel, Wei Sun
  • Patent number: 11928353
    Abstract: A processing device, operatively coupled with a memory device, is configured to perform a write operation on a page of a plurality of pages of a data unit of a memory device. The processing device further generates a parity page for data stored in the page of the data unit and associates the parity page with parity data associated with the data unit. Responsive to determining that a first size of the parity data is larger than a first threshold size, the processing device compresses the parity data. Responsive to determining that a second size of the compressed parity data is larger than a second threshold size, the processing device releases at least a subset of the parity data corresponding to a subset of the data that is free from defects.
    Type: Grant
    Filed: January 18, 2023
    Date of Patent: March 12, 2024
    Assignee: Micron Technology, Inc.
    Inventors: Harish R Singidi, Ashutosh Malshe, Vamsi Pavan Rayaprolu, Kishore Kumar Muchherla
  • Patent number: 11922047
    Abstract: One example method includes ingesting data to a data protection system, separating, by the data protection system, the ingested data into groups according to Recovery Point Objective (RPO) such that each group is associated with a different respective RPO, storing the groups in respective storage pools, and each of the storage pools is associated with a respective one of the RPOs, and performing a respective garbage collection (GC) process at each storage pool.
    Type: Grant
    Filed: September 16, 2021
    Date of Patent: March 5, 2024
    Assignee: EMC IP Holding Company LLC
    Inventors: Anand Rudrabhatla, Jehuda Shemer, Abhinav Duggal
  • Patent number: 11907536
    Abstract: A method includes determining a respective number of and respective locations of valid data portions of a plurality of blocks of NAND memory cells, based on the respective locations of the valid data portions, determining respective dispersions of the valid data portions within the plurality of blocks of NAND memory cells, based at least on the respective dispersions, selecting a block of NAND memory cells from the plurality of blocks of NAND memory cells, and performing a folding operation on the selected block.
    Type: Grant
    Filed: January 4, 2023
    Date of Patent: February 20, 2024
    Assignee: Micron Technology, Inc.
    Inventors: Ashutosh Malshe, Vamsi Pavan Rayaprolu, Kishore K. Muchherla
  • Patent number: 11907564
    Abstract: A method and system for initiating a garbage collection request. Historical data representative of a level of initiated I/O requests is acquired. A first operational state and a second operational state are determined based on the historical data. The first operational state and second operational state are expressed in an indication of the level of initiated I/O requests to be processed. A number of currently initiated I/O requests is acquired. A determination is made as to whether the number of currently initiated I/O requests is indicative of the first operational state or the second operational state. If the computer system is in the first operational state, the garbage collection request is initiated.
    Type: Grant
    Filed: August 3, 2021
    Date of Patent: February 20, 2024
    Assignee: YADRO INTERNATIONAL LTD.
    Inventor: Viacheslav Dubeyko
  • Patent number: 11899575
    Abstract: This disclosure provides for host-controller cooperation in managing NAND flash memory. The controller maintains information for each erase unit which tracks memory usage. This information assists the host in making decisions about specific operations, for example, initiating garbage collection, space reclamation, wear leveling or other operations. For example, metadata can be provided to the host identifying whether each page of an erase unit has been released, and the host can specifically then command each of consolidation and erase using direct addressing. By redefining host-controller responsibilities in this manner, much of the overhead association with FTL functions can be substantially removed from the memory controller, with the host directly specifying physical addresses. This reduces performance unpredictability and overhead, thereby facilitating integration of solid state drives (SSDs) with other forms of storage.
    Type: Grant
    Filed: December 1, 2022
    Date of Patent: February 13, 2024
    Assignee: Radian Memory Systems, Inc.
    Inventors: Andrey V. Kuzmin, Mike Jadon, Richard M. Mathews
  • Patent number: 11893265
    Abstract: Methods, systems, apparatus, including computer programs encoded on computer storage media, for reclaiming storage space in a storage environment. In one aspect, the method includes actions of aggregating data that is indicative of access to one or more data objects, determining a future storage cost associated with each of a plurality of data objects, determining an access window for each of the plurality of data objects, identifying a data object based on (i) the future storage cost that satisfies a predetermined threshold and (ii) a data object access window, providing a notification to a user device that requests feedback from a user indicating whether the data object can be deleted, and in response to receiving data that indicates that the data object can be deleted, generating an instruction to cause deletion of the data object upon the expiration of the access window.
    Type: Grant
    Filed: March 26, 2022
    Date of Patent: February 6, 2024
    Assignee: Google LLC
    Inventors: Konstantinos Nikoloudakis, Sven Koehler, Danyao Wang, Sahand Saba, Long Fei, Simon Tyler Wise, David Halladay Schneider
  • Patent number: 11886735
    Abstract: Methods, systems, and devices for data movement based on address table activity are described. A memory system may support a first type of data movement operation and a second type of data movement operation. The memory system may select between the first type of data movement operation and the second type of data movement operation for a region based on address table activity for the region.
    Type: Grant
    Filed: March 22, 2022
    Date of Patent: January 30, 2024
    Assignee: Micron Technology, Inc.
    Inventor: Yanhua Bi
  • Patent number: 11874753
    Abstract: Systems, apparatuses, and methods related log compression are described. In an example, a system log that identifies targeted data may be compiled in a memory resource during an execution of an operation using that memory resource. The system log may be analyzed utilizing a portion of the memory resource that would otherwise be available to be utilized in the execution of the operation. The system log may be compressed during the execution of the operation, the level or timing of such compression may be based on the analysis that occurs contemporaneous to or as a result of executing the operation. In some examples, compressing the system log may include discarding a portion of the system log. Compressing the system log may also include extracting the targeted data from the system log as the system log is being compiled and converting the extracted targeted data to structured data.
    Type: Grant
    Filed: October 17, 2022
    Date of Patent: January 16, 2024
    Assignee: Micron Technology, Inc.
    Inventors: Reshmi Basu, Libo Wang
  • Patent number: 11868642
    Abstract: Disclosed is a system that comprises a memory device and a processing device, operatively coupled with the memory device, to perform operations that include receiving, by the processing device, a trim command on the memory device, wherein the trim command references a range of logical block addresses (LBAs). The operations performed by the processing device further include identifying a group of memory cells corresponding to the range of LBAs, wherein the group of memory cells comprises one or more management units (MUs). The operations performed by the processing device further include updating a data structure associated with the group of memory cells to reference the request; receiving a memory access command with respect to the group of memory cells.
    Type: Grant
    Filed: August 31, 2021
    Date of Patent: January 9, 2024
    Assignee: Micron Technology, Inc.
    Inventors: Yueh-Hung Chen, Fangfang Zhu, Horia Simionescu, Chih-Kuo Kao, Jiangli Zhu
  • Patent number: 11853208
    Abstract: A storage device includes a nonvolatile memory, a volatile memory, and a controller accesses the nonvolatile memory using an address conversion table including regions, each region including entries, each entry storing a physical address of the nonvolatile memory in association with a logical address, and reads and writes data of the address conversion table from and to the nonvolatile memory and the volatile memory in a unit of a frame. The controller writes, to the nonvolatile memory, data of a first region in a first format in which a head address of data of a region aligns with a head address of a frame, and writes, to the volatile memory, data of a second region in either the first format or a second format in which a head address of data of a region does not align with a head address of a frame.
    Type: Grant
    Filed: December 19, 2022
    Date of Patent: December 26, 2023
    Assignee: Kioxia Corporation
    Inventors: Akinori Nagaoka, Mitsunori Tadokoro
  • Patent number: 11847334
    Abstract: Methods and systems for managing data in a distributed system are disclosed. The distributed system may include devices used by users (e.g., clients) and devices in which data is stored for future accessibility (e.g., storage providers). A data storage system may manage the data for the clients. To manage the data efficiently, the data storage system may perform an integrated process of both verifying that segments of files believed to be stored are actually stored and segments of files that no longer need to be stored are removed. The process may not be performed in real-time as files that no longer need to be stored are identified (e.g., as deletion requests are received). Rather, the integrated process may employ a garbage collection process where deletion conditions for segments are checked intermittently over time, and files are verified.
    Type: Grant
    Filed: September 23, 2021
    Date of Patent: December 19, 2023
    Assignee: EMC IP HOLDING COMPANY LLC
    Inventors: Rahul Goyal, Tony Wong
  • Patent number: 11847347
    Abstract: The present invention relates to a VCRM data transmission optimizing method and an apparatus therefor, and a method of transmitting VCRM data in a vehicle terminal may include generating at least one data slot buffer, determining whether to perform buffer flush according to whether data is changed, and whether a buffer max size is reached, when new data is entered, and flushing data recorded in a corresponding data slot buffer according to the determination for performing the buffer flush to be transmitted to a server over a wireless network.
    Type: Grant
    Filed: October 8, 2021
    Date of Patent: December 19, 2023
    Assignees: HYUNDAI MOTOR COMPANY, KIA CORPORATION
    Inventor: Sun Woo Kim
  • Patent number: 11836368
    Abstract: A lossy method of compressing data, such as image data, which uses wrap-around wavelet compression is described. Each data value is divided into two parts and the first parts, which comprise the most significant bits from the data values, are compressed using wrap-around wavelet compression. Depending upon the target compression ratio and the compression ratio achieved by compressing just the first parts, none, one or more bits from the second parts, or from a data value derived from the second parts, may be appended to the compressed first parts. The method described may be lossy or may be lossless. A corresponding decompression method is also described.
    Type: Grant
    Filed: November 29, 2022
    Date of Patent: December 5, 2023
    Assignee: Imagination Technologies Limited
    Inventors: Linling Zhang, Simon Fenney
  • Patent number: 11829600
    Abstract: A storage system includes an interface and a data compression system configured to compress reception data from the interface before the data is stored in a storage device. The data compression system is configured to compress the reception data using a first compression algorithm to generate first compressed data, use the number of appearances of each of predetermined code categories included in the first compressed data to estimate a decompression time when a second compression algorithm is used, select a second compression method including compression using the second compression algorithm when the decompression time is equal to or less than a threshold value, and select a first compression method that does not include the compression using the second compression algorithm when the decompression time is greater than the threshold value.
    Type: Grant
    Filed: March 8, 2022
    Date of Patent: November 28, 2023
    Assignee: HITACHI, LTD.
    Inventors: Nagamasa Mizushima, Kentaro Shimada
  • Patent number: 11816349
    Abstract: A system and apparatus for secure NVM format by pre-erase is disclosed. According to certain embodiments when an NVM does into idle mode, one or more free blocks are serially popped from a free block heap. The free block is then physically erased in an SLC mode, and then pushed to a pre-erase heap. The process is performed in both SLC and TLC partitions, in the TLC partition the block becomes hybrid SLC (HSLC). This process increases a program erase count (PEC) value of the block, maintaining device longevity. When there is a need to use a new block, it is popped from the pre-erase heap. In some cases where there is a need to use a TLC block instead of an HSLC block, an erase operation is used that converts the block from HSLC to TLC, and does not increase a PEC value for the block.
    Type: Grant
    Filed: November 3, 2021
    Date of Patent: November 14, 2023
    Assignee: Western Digital Technologies, Inc.
    Inventors: Lola Grin, Itay Busnach, Micha Yonin, Lior Bublil
  • Patent number: 11797204
    Abstract: A data processing method includes obtaining a plurality of data blocks, determining a first data block and a second data block from the data blocks, where the first data block has a first hash value, and the second data block has a second hash value, where the first hash value is obtained by performing calculation on the first data block based on a hash algorithm and the second hash value is obtained by performing calculation on the second data block based on the hash algorithm, and combining and compressing the first data block and the second data block based on a degree of similarity of the first data block and the second data block.
    Type: Grant
    Filed: September 2, 2021
    Date of Patent: October 24, 2023
    Assignee: HUAWEI TECHNOLOGIES CO., LTD.
    Inventors: Siwei Luo, Dong Qiu, Rui Qian