Patents Examined by Christopher D Birkhimer
  • Patent number: 11327672
    Abstract: A data storage device may include a storage including a plurality of dies each including a plurality of memory blocks including a plurality of pages, and a controller configured to select at least one memory block from each of the dies to configure a block group, configure a page group with pages having an equal offset in each memory block in each block group, and access the storage in a die interleaving manner. The controller may be configured to detect an open block group as power is supplied after sudden power off, set search sections for each die including a plurality of blocks in the detected open block group, and search for a last access page by simultaneously accessing the search sections for each die.
    Type: Grant
    Filed: December 6, 2019
    Date of Patent: May 10, 2022
    Assignee: SK hynix Inc.
    Inventor: Jong Hwan Lee
  • Patent number: 11320890
    Abstract: Techniques and apparatuses are described that enable power-conserving cache memory usage. Main memory constructed using, e.g., DRAM can be placed in a low-power mode, such as a self-refresh mode, for longer time periods using the described techniques and apparatuses. A hierarchical memory system includes a supplemental cache memory operatively coupled between a higher-level cache memory and the main memory. The main memory can be placed in the self-refresh mode responsive to the supplemental cache memory being selectively activated. The supplemental cache memory can be implemented with a highly- or fully-associative cache memory that is smaller than the higher-level cache memory. Thus, the supplemental cache memory can handle those cache misses by the higher-level cache memory that arise because too many memory blocks are mapped to a single cache line. In this manner, a DRAM implementation of the main memory can be kept in the self-refresh mode for longer time periods.
    Type: Grant
    Filed: July 6, 2020
    Date of Patent: May 3, 2022
    Assignee: Google LLC
    Inventor: Christopher J. Phoenix
  • Patent number: 11314430
    Abstract: Techniques read data. Such techniques involve: in response to receiving a read request from the user for data on a physical data block, determining whether there is data state information corresponding to the physical data block. The data state information may include a plurality of units for respectively indicating availability of data stored in a plurality of sub-blocks of the physical data block. Such techniques further involve: in response to determining that there is data state information, selecting a target sub-block from the plurality of sub-blocks of the physical storage block based on the data state information. Such techniques further involve: providing the user with data stored in the target sub-block. Such techniques are capable of determining the availability of data at a finer granularity.
    Type: Grant
    Filed: October 18, 2019
    Date of Patent: April 26, 2022
    Assignee: EMC IP Holding Company LLC
    Inventors: Lifeng Yang, Xiongcheng Li, Xinlei Xu
  • Patent number: 11314438
    Abstract: An arithmetic processing device includes an arithmetic circuit and a memory access controller performing access control for a read request on a memory module including a volatile memory and a nonvolatile memory, the volatile memory operating as a cache of the nonvolatile memory. The memory access controller stores an address table on which unit addresses including a request address of the read request are registered, issues a speculative read to the memory module in response to the read request and update the address table when the request address is included in the unit addresses in the address table, and issues a normal read when the request address is not included in any of the unit addresses. When the normal read is issued, read data is received after transmitting a transmission request signal. When the speculative read is issued, read data are acquired when receiving a hit flag.
    Type: Grant
    Filed: November 26, 2019
    Date of Patent: April 26, 2022
    Assignee: FUJITSU LIMITED
    Inventor: Shinichi Iwasaki
  • Patent number: 11301373
    Abstract: A storage device includes a nonvolatile memory including a plurality of physical blocks, a communication interface connectable to a host, and a controller. The controller is configured to generate metadata of host data, which include user data and metadata of the user data, and write, in a physical block of the nonvolatile memory, the metadata of the host data, the metadata of the user data, and the user data continuously in this order, when the host data are received through the communication interface in association with a write command.
    Type: Grant
    Filed: November 30, 2020
    Date of Patent: April 12, 2022
    Assignee: KIOXIA CORPORATION
    Inventors: Daisuke Hashimoto, Shigehiro Asano, Katsuhiko Ueki, Mark Hayashida
  • Patent number: 11287999
    Abstract: A multi-instance 2-Level-Memory (2LM) architecture manages access by processing instances having different memory usage priorities to memory having different performance and cost levels. The 2LM architecture includes a virtual memory management module that manages access by respective processing instances by creating memory instances based on specified memory usage priority levels and specified virtual memory sizes and defining policies for each usage priority level of the created memory instances. In response to a virtual memory request by a processing instance, the virtual memory management module determines whether a virtual memory size at a designated usage priority level requested by a processing instance can be satisfied by a policy of a created first memory instance and, if not, selects another memory instance that can satisfy the requested virtual memory size at the designated usage priority level and swaps out the first memory instance in favor of the other memory instance.
    Type: Grant
    Filed: June 9, 2020
    Date of Patent: March 29, 2022
    Assignee: Huawei Technologies Co., Ltd.
    Inventors: Chaohong Hu, Zhou Yu
  • Patent number: 11269773
    Abstract: Circuitry comprises a set of two or more data handling nodes each having respective storage circuitry to hold data; and a home node to serialise data access operations and to control coherency amongst data held by the one or more data handling nodes so that data written to a memory address is consistent with data read from that memory address in response to a subsequent access request; in which: a requesting node of the set of data handling nodes is configured to communicate a request to the home node for exclusive access to a given instance of data at a given memory address; and the home node is configured, in response to the request, to communicate information to other data handling nodes of the set of data handling nodes to control handling, by those other data handling nodes, of any further instances of the data at the given memory address which are held by those other data handling nodes.
    Type: Grant
    Filed: October 8, 2019
    Date of Patent: March 8, 2022
    Assignee: Arm Limited
    Inventors: Bruce James Mathewson, Phanindra Kumar Mannava, Jamshed Jalal, Klas Magnus Bruce, Andrew John Turner
  • Patent number: 11249644
    Abstract: A computer-implemented method, according to one embodiment, is for integrating magnetic tape storage with a distributed disk file system. The computer-implemented method includes: registering for a subset of data operations that are recorded at a central location, where the central location is coupled to a plurality of distributed accessor nodes. A subset of available resources in one or more magnetic tape libraries that are coupled to the plurality of distributed accessor nodes are registered for and further managed. Moreover, a performance of the subset of data operations using the registered subset of available resources is scheduled. Supplemental data operations which correspond to the subset of data operations are also automatically received from the central location.
    Type: Grant
    Filed: September 18, 2019
    Date of Patent: February 15, 2022
    Assignee: International Business Machines Corporation
    Inventors: Slavisa Sarafijanovic, Martin Petermann, Bo Zou, Jin Yin, Feng Shao, Jiong Lu, Ning Wang
  • Patent number: 11237740
    Abstract: Methods, apparatus, and processor-readable storage media for automatically determining sizing configurations for storage components using machine learning techniques are provided herein. An example computer-implemented method includes obtaining multiple items of input related to at least one storage component; determining a set of storage component sizing configurations by processing at least a portion of the multiple items of input using a first set of one or more machine learning techniques comprising at least one deep learning technique; identifying a subset of the storage component sizing configurations by processing at least a portion of the determined set of storage component sizing configurations using a second set of one or more machine learning techniques; and performing one or more automated actions based at least in part on the identified subset of storage component sizing configurations.
    Type: Grant
    Filed: January 31, 2020
    Date of Patent: February 1, 2022
    Assignee: EMC IP Holding Company LLC
    Inventors: Bina K. Thakkar, Deepak Gowda, Wenjin Liu
  • Patent number: 11216383
    Abstract: An electronic system includes a host device and a storage device including a first memory device of a volatile type and a second memory device of a nonvolatile type. The first memory device is accessed by the host device through a memory-mapped input-output interface and the second memory device is accessed by the host device through a block accessible interface. The storage device provides a virtual memory region to the host device such that a host-dedicated memory region having a first size included in the first memory device is mapped to the virtual memory region having a second size larger than the first size.
    Type: Grant
    Filed: March 4, 2019
    Date of Patent: January 4, 2022
    Assignee: SAMSUNG ELECTRONICS CO., LTD.
    Inventors: Duck-Ho Bae, Dong-Uk Kim, Hyung-Woo Ryu, Kwang-Hyun La, Joo-Young Hwang, You-Ra Choi
  • Patent number: 11209987
    Abstract: A storage system and an access control method thereof are provided. The storage system receives a first I/O request from at least one hypervisor. The first I/O request is used for accessing a first disk file of disk files. The storage system then operates a first I/O operation of a first virtual disk of virtual disks according to the first I/O request since the disk files correspond to the virtual disks. The storage system reads a QoS data of the first disk file and determines a first delay period according to the QoS data. The storage system transmits a first I/O response to the at least one hypervisor after the first delay period.
    Type: Grant
    Filed: February 20, 2014
    Date of Patent: December 28, 2021
    Assignee: Silicon Motion Technology (Hong Kong) Limited
    Inventors: Kuan-Kai Chiu, Tsung-Lin Yu
  • Patent number: 11194502
    Abstract: A flash memory controller is configured to access a flash memory module, and the flash memory controller includes a read-only memory and a microprocessor. When the flash memory controller is powered on and performs an initialization operation, within a predetermined time range of the initialization operation, the microprocessor determines whether a number of spare blocks in the flash memory module is lower than a first threshold value to determine whether to perform a garbage collection operation. When an elapsed time since the flash memory controller is powered on exceeds the predetermined time range, the microprocessor determines whether a number of spare blocks in the flash memory module is lower than a second threshold to determine whether to perform another garbage collection operation, where the second threshold value is lower than the first threshold.
    Type: Grant
    Filed: October 28, 2020
    Date of Patent: December 7, 2021
    Assignee: Silicon Motion, Inc.
    Inventor: Wen-Sheng Lin
  • Patent number: 11194496
    Abstract: Deduplication functionality is provided for a key-value solid-state drive (KVSSD) that includes a storage space and a controller. The storage space contains first and second containers. The first container includes a first virtual space and stores a key and at least one dedup key associated with the key. Each dedup key corresponds to a block of user data, and each block includes a predetermined size. The second container includes a second virtual space and stores each dedup key, the block of user data associated with the dedup key and metadata associated with the block of user data. The controller determines whether a block of user data received by the KVSSD is a duplicate block of data stored in the second container by determining whether a dedup key for the received block of user data matches a stored dedup key in the first container.
    Type: Grant
    Filed: December 17, 2019
    Date of Patent: December 7, 2021
    Inventors: Kumar Kanteti, Vishwanath Maram
  • Patent number: 11163448
    Abstract: Adjusting storage capacity in a computing system that includes a computing device configured to send access requests to a storage device characterized by a first storage capacity, including: reducing data; determining, in dependence upon an amount of storage capacity saved by reducing the data, an updated storage capacity for the storage device; and exporting an updated storage capacity to the computing device.
    Type: Grant
    Filed: August 29, 2019
    Date of Patent: November 2, 2021
    Assignee: PURE STORAGE, INC.
    Inventor: John Colgrove
  • Patent number: 11163691
    Abstract: Examples of the present disclosure relate to an apparatus comprising processing circuitry to perform data processing operations, storage circuitry to store data for access by the processing circuitry, address translation circuitry to maintain address translation data for translating virtual memory addresses into corresponding physical memory addresses, and prefetch circuitry. The prefetch circuitry is arranged to prefetch first data into the storage circuitry in anticipation of the first data being required for performing the data processing operations. The prefetching comprises, based on a prediction scheme, predicting a first virtual memory address associated with the first data, accessing the address translation circuitry to determine a first physical memory address corresponding to the first virtual memory address, and retrieving the first data based on the first physical memory address corresponding to the first virtual memory address.
    Type: Grant
    Filed: June 25, 2019
    Date of Patent: November 2, 2021
    Assignee: ARM LIMITED
    Inventors: Stefano Ghiggini, Natalya Bondarenko, Damien Guillaume Pierre Payet, Lucas Garcia
  • Patent number: 11163463
    Abstract: A virtual volume is initially provided from a first storage appliance within a cluster of storage appliances by providing access to the virtual volume over a data path between a host computer and a protocol endpoint hosted on the first storage appliance, based on an initial binding between the virtual volume and the protocol endpoint hosted on the first storage appliance. A rebind request is conveyed to the host computer, and in response to receiving a bind request for the virtual volume, a new binding is created between the virtual volume and a protocol endpoint hosted by the second storage appliance. The virtual volume is subsequently provided from the second storage appliance by providing the host computer with access to the virtual volume over a data path between the host computer and the protocol endpoint hosted on the second storage appliance based on the newly created binding.
    Type: Grant
    Filed: July 27, 2020
    Date of Patent: November 2, 2021
    Assignee: EMC IP Holding Company LLC
    Inventors: Dmitry Tylik, Vinod Rajasekaran, Anil K. Koluguri, Matthew H. Long
  • Patent number: 11157171
    Abstract: Systems and methods for migrating stored backup data between disks (e.g., from an existing disk to another disk), such as a new or different disk in a magnetic storage library, without interrupting or otherwise affecting secondary copy operations (e.g., operations currently writing data to the storage library) utilizing the magnetic storage library, are described. In some embodiments, the systems and methods mark one or more mount paths as full when a running secondary copy operation associated with the mount path has completed a job (regardless of the actual current capacity or intended use of the mount path), and migrate each of the one or more data to a second disk of the data storage library when the mount path associated with the data is marked as full.
    Type: Grant
    Filed: April 24, 2020
    Date of Patent: October 26, 2021
    Assignee: Commvault Systems, Inc.
    Inventors: Jaidev Oppath Kochunni, Michael Frank Klose
  • Patent number: 11137937
    Abstract: A master issues the valid data is specified when the data update processing is interrupted. The control unit 3 stores in the storage unit 2 the second update status flag 8_2, which indicates the update status of the first update status flag 8_1 and the second data 6_2, which indicate the update status of the first data 6_1, and the third update status flag 8_3, which indicates the update status of the valid indication flag 7. When the determination based on the valid instruction flag 7 is impossible, the usage data determination unit 4 determines which of the first data 6_1 and the second data 6_2 is valid based on the values of the first update status flag 8_1, the second update status flag 8_2, and the third update status flag 8_3.
    Type: Grant
    Filed: June 24, 2019
    Date of Patent: October 5, 2021
    Assignee: RENESAS ELECTRONICS CORPORATION
    Inventors: Takashi Kurafuji, Satoshi Yamamoto
  • Patent number: 11119674
    Abstract: A memory device includes an array of composite memory units. At least one of the composite memory units comprises a first memory cell of a first type, a second memory cell of a second type, a first intra-unit data path connecting the first memory cell to the second memory cell, and a first data path control switch. The first data path control switch is responsive to a data transfer enable signal which enables data transfer between the first memory cell and the second memory cell through the first intra-unit data path.
    Type: Grant
    Filed: February 19, 2019
    Date of Patent: September 14, 2021
    Assignee: MACRONIX INTERNATIONAL CO., LTD.
    Inventors: Hung-Sheng Chang, Han-Wen Hu
  • Patent number: 11113158
    Abstract: A new snapshot of a storage volume is created by instructing computing nodes to suppress write requests. An orchestration layer implements a multi-role application that is provisioned with virtualized storage and computation resources. A snapshot of the application may be created and used to rollback or clone the application. Clones snapshots of storage volumes may be thin clones. An application may use multiple orchestration approaches and objects of the multi-role application may be discovered and added to an application definition. The application definition may be used to create snapshots of the application and perform operations using the snapshots. Rolling back may include deleting objects other than PVCs, followed by rolling back storage volumes mounted to the PVCs, followed by recreating objects according to an application snapshot. PVCs created by a custom resource may be deleted along with the custom resource with the PVCs being recreated before recreating the custom resource.
    Type: Grant
    Filed: October 4, 2019
    Date of Patent: September 7, 2021
    Assignee: ROBIN SYSTEMS, INC.
    Inventors: Ravi Kumar Alluboyina, Sree Nandan Atur