Abstract: GaN-based half bridge power conversion circuits employ control, support and logic functions that are monolithically integrated on the same devices as the power transistors. In some embodiments a low side GaN device communicates through one or more level shift circuits with a high side GaN device. Both the high side and the low side devices may have one or more integrated control, support and logic functions. Some devices employ electro-static discharge circuits and features formed within the GaN-based devices to improve the reliability and performance of the half bridge power conversion circuits.

Abstract: In an example, an apparatus includes an analog switch having an n-type metal oxide semiconductor (NMOS) circuit in parallel with a p-type metal oxide semiconductor (PMOS) circuit between a switch input and a switch output. The analog switch is responsive to an enable signal that determines switch state thereof. The NMOS circuit includes a switch N-channel transistor coupled to a buffer N-channel transistor, a gate of the switch N-channel transistor coupled to the enable signal and a gate of the buffer N-channel transistor coupled to a modulated N-channel gate voltage. The PMOS circuit including a switch P-channel transistor coupled to a buffer P-channel transistor, a gate of the switch P-channel transistor coupled to a complement of the enable signal and a gate of the buffer P-channel transistor coupled to a modulated P-channel gate voltage.

Abstract: A method is used to control an electronic device that includes a switching unit having a main MOS transistor having a substrate, a first conducting electrode and a second conducting electrode coupled to an output terminal. The method includes controlling the main transistor in such a way as to put it into an on state or an off state such that, when the main transistor is in the on state, the substrate and the first conducting electrode of the main transistor are connected to an input terminal and, when the main transistor is in the off state, the first conducting electrode of the main transistor is isolated from the input terminal and a first bias voltage is applied to the first conducting electrode and a second bias voltage is applied to the substrate of the main transistor.

Abstract: A circuit has first and second semiconductor switches, each of which has a load path and control terminal connected in series. Each switch includes a first semiconductor device having a load path and a control terminal coupled to the control terminal of its switch, and a second semiconductor device having a load path between first and second load terminals, and a control terminal. Each second semiconductor device has its load path connected in series to the load path of the corresponding first semiconductor device. The semiconductor devices are coupled such that the second semiconductor devices are controlled by a load path voltage of the first semiconductor devices. The switches are integrated in a common semiconductor body. The first switch is implemented in a first area of the semiconductor body, and the second switch is implemented in a second area. In a horizontal plane, the first area surrounds the second area.

Abstract: A semiconductor integrated circuit includes an output circuit driven by a power voltage across a first and a second node. A control circuit is driven by the power voltage to control output a digital signal at a pad terminal, a logic value of the signal being set by a core circuit connected to the output circuit. The digital signal causes a voltage at the first node to be high and a voltage at the second node to low when a predetermined power voltage higher than a withstanding voltage of the output circuit is applied across the first and second nodes. The control circuit controls voltages across terminals of switching elements in the output circuit to be less than their withstanding voltages and to prevent current flowing from the pad terminal to the output circuit when the first power node is in a high impedance state.

Abstract: A semiconductor device includes a gate terminal, a ground terminal, a power-supply terminal, and a source terminal. The semiconductor device includes a first switch element having a gate and a source, the first switch element connected between the gate terminal and the source terminal, a second switch element connected between one of the gate of the first switch element and the source terminal or between the gate of the first switch element and the ground terminal and configured to switch the first switch element between turned-on and turned-off states, and a capacitor having one terminal thereof connected to the power-supply terminal and the ground terminal and another terminal thereof connected to the gate of the first switch element. Based on the potential state of the ground terminal and the state of the second switch element, the capacitor boosts the voltage of the gate of the first switch element.

Abstract: A voltage level translation circuit includes a first energy storage unit, a second energy storage unit, a first voltage level translation unit, and a second voltage level translation unit. The first voltage level translation unit is configured to translate a first communication interface transmitting pin voltage signal to realize a first communication between a first communication interface transmitting pin and a second communication interface receiving pin. The second voltage level translation unit is configured to translate a second communication interface transmitting pin voltage signal to realize a second communication between a second communication interface transmitting pin and a first communication interface receiving pin. A multiple interface communication system is also provided.

Abstract: An LED driver design has a single controller used to drive multiple strings of LEDs. In one aspect there is dynamic threshold voltage setting so that the individual characteristics of the LED strings can be taken into account in the voltage control loop. In another aspect, excess energy is dissipated off-chip in a dedicated heat dissipater, and the routing of current to the heat dissipater is controlled dynamically such that a desired integrated circuit biasing remains stable.

Abstract: Circuits, apparatuses, and methods are disclosed for frequency division. In one such example circuit, a frequency divider is configured to alternate between providing a common frequency clock signal as an output clock signal through a first circuit responsive to a reference clock signal and providing a reduced frequency clock signal as the output clock signal through a second circuit responsive to the reference clock signal. The first and second circuits share a shared circuit through which the output clock signal is provided. An enable circuit is configured to cause the frequency divider to alternate between providing the common frequency clock signal as the output clock signal through the first circuit and the reduced frequency clock signal as the output clock signal through the second circuit.

Abstract: A transistor monolithically integrated in a semiconductor body includes a first sub-transistor and a second sub-transistor that both include a first and second load contacts and a control contact for controlling an electric current through a load path. The first load contact of the first sub-transistor is electrically connected to the first load contact of the second sub-transistor and the second load contact of the first sub-transistor is electrically connected to the second load contact of the second sub-transistor. A control circuit is configured to cause the first sub-transistor to switch from a first state to a second state at a first point of time and to cause the second sub-transistor to switch from the first state to the second state at a second point of time subsequent to the first point of time.

Abstract: A circuit architecture and process that provides for a dual-mode methodology for an RF integrated circuit (IC) switch circuit that allows switching between a direct mapping configuration and a fully decoded mapping configuration, and further provides for changing either mapping configuration after fabrication. A control word is selectively compared to a programmed map register value so that, in a first mode, only one bit position of a control word matches a decoded programmed map bit pattern, and in a second mode, all bits of a control word match a corresponding programmed map bit pattern. Because the map registers can be programmed at least once after IC fabrication, the exact mapping required for a particular application can be determined post fabrication. Further, the first mode of operation is often beneficial during testing because multiple RF signal paths can be turned on at the same time and thus tested in parallel.

Abstract: An integrated circuit controls one or more external back-to-back (anti-series) transistor switches with three pins per switch. Two pins couple the switch terminals of the external switch to terminals of an internal anti-series switch. An intermediate source node of the internal switch provides a reference voltage that is representative of the external switch's intermediate source node. A predriver of the integrated circuit drives a gate signal relative to the reference voltage, enabling fast, non-dissipative switching of the external switch. A disclosed method includes coupling switch terminal signals from an external anti-series switch to terminals of an internal anti-series switch; and driving a gate signal to the external anti-series switch relative to a reference voltage of an intermediate node of the internal anti-series switch.

Abstract: An electronic device having at least a first HEMT transistor and bias circuit able to at least reverse bias the first HEMT transistor by applying an electric voltage VSD of a positive value between a source of the first HEMT transistor and a drain of the first HEMT transistor. The first HEMT transistor is able to be ON when a value of an electric voltage VGD between a gate of the first HEMT transistor and the drain of the first HEMT transistor is higher than a value of a threshold voltage Vth of the first HEMT transistor. The electronic device has, during a forward biasing, a behavior similar to that of a forward biased or reverse biased Zener diode.

Abstract: Described are embodiments of stacked field effect transistor (FET) switch having a plurality of FET devices coupled in series to form an FET device stack. To prevent the FET device stack from being turned on during large signal conditions, a first decoupling path and a second decoupling path are provided for the first FET device and the last FET device in the FET device stack. Both decoupling paths are configured to pass a time-variant input signal during the open state. The first decoupling path may be coupled from the drain contact of the first FET device to the gate contact or the source contact. The second decoupling path may be coupled from the source contact of the last FET device to the gate contact or drain contact. The time-variant input signal bypasses the FET device stack through the first and second decoupling paths during the open state.

Abstract: A method of differential signal transfer from a differential input Vinp and Vinn having a common mode input voltage that can be higher than the power supply voltage by providing an input chopper having first through fourth chopper transistors, each having a source, a drain and a gate, the input chopper having Vinp and Vinn as a differential input, providing an output chopper, capacitively coupling a differential output Voutp and Voutn of the input chopper to a differential input of the output chopper, capacitively coupling a clock to the input chopper and coupling the clock to the output chopper, the clock having a first phase and a second phase opposite from the first phase, the first phase being coupled to the gates of the first and second transistors and the second phase being coupled to the gates of the third and fourth transistors, and providing protection of the gates of the first through fourth transistors from excessive voltages. Various embodiments are disclosed.

Abstract: An on-chip true noise generator including an embedded noise source with a low-voltage, high-noise zener diode(s), and an in-situ close-loop zener diode power control circuit. The present invention proposes the use of heavily doped polysilicon and silicon p-n diode(s) structures to minimize the breakdown voltage, increasing noise level and improving reliability. The present invention also proposes an in-situ close-loop zener diode control circuit to safe-guard the zener diode from catastrophic burn-out.

Abstract: Radio-frequency (RF) devices are disclosed having transistor gate voltage compensation to provide improved switching performance. RF devices, such as switches, include a plurality of field-effect transistors (FETs) connected in series between first and second nodes, each FET having a gate. A compensation network including a coupling circuit couples the gates of each pair of neighboring FETs.

Abstract: Switching circuitry for use in a digital-to-analog converter, the circuitry comprising: a common node; first and second output nodes; and a plurality of switches connected between the common node and the first and second output nodes and operable in each clock cycle of a series of clock cycles, based on input data, to conductively connect the common node to either the first or second output node along a given one of a plurality of paths, wherein the circuitry is arranged such that a data-controlled switch and a clock-controlled switch are provided in series along each said path from the common node to the first or second output node.

Abstract: A power-gate circuit includes a power-gate transistor operable to switch to decouple a first supply voltage from a second supply voltage during an idle mode, and to couple the first supply voltage to the second supply voltage during a full operational mode. Part of the charge stored at a gate terminal of the power-gate transistor, would have been otherwise flushed to ground while turning on the power-gate transistor, is routed to the rail of the second supply voltage of the logic block. Part of the charge on the rail of the second supply voltage is used to charge the gate terminal of the power-gate transistor to deactivate the power-gate transistor if the logic block goes to the idle mode. Energy is saved both ways because of the charge recycling and the ability to use the power gate circuit even in cases where the duration of the idle mode may be short.

Abstract: A CMOS transmission gate that is compensated for lost current to parasitic capacitance. Parasitic capacitance current is detected by an amplifier and fed back in-phase to the input of the CMOS transmission gate with the gain of the amplifier set to avoid circuit instability. In a first example a transconductance amplifier detects a voltage drop across a resistor in and RC network and the resulting current applied to the input of the transmission gate. A second example uses a current amplifier to detect gate current of the N-channel and P-channel transistors of the transmission gate, and an output current is fed back in phase to the input of the CMOS transmission gate.