Patents Examined by Colleen O'Toole
  • Patent number: 9711189
    Abstract: A buffer circuit with an adjustable reference voltage is presented. The buffer circuit with adjustable reference voltage has an input buffer circuit that is connected to a data input and a reference voltage. The output of the input buffer circuit is connected an eye monitor circuit that generates a transition signal based on a number of transitions of an output of the input buffer circuit. The output from the eye monitor circuit is that processed by a calibration control circuit that transmits a selection signal to a multiplexer. The multiplexer selects a level of the reference voltage based on the selection signal from the calibration control circuit.
    Type: Grant
    Filed: August 12, 2011
    Date of Patent: July 18, 2017
    Assignee: Altera Corporation
    Inventors: Bonnie I. Wang, Chiakang Sung, Xiaobao Wang, Yan Chong, Joseph Huang, Khai Nguyen, Pradeep Nagarajan
  • Patent number: 9698783
    Abstract: Provided is a configuration of a driver integrated circuit that can output a voltage exceeding the withstand voltage of a process, and that satisfies required apparatus performance (high speed and high voltage). A differential input circuit, a level shift circuit, and an output circuit are manufactured by the same process and divided and disposed on three or more chips with different substrate potentials (sub-potentials). By setting different applied voltages to the substrates of the chips, an output voltage greater than the process withstand voltage can be provided (see FIG. 2).
    Type: Grant
    Filed: May 24, 2012
    Date of Patent: July 4, 2017
    Assignee: Hitachi, Ltd.
    Inventors: Wen Li, Norio Chujo, Masami Makuuchi, Takehito Kamimura
  • Patent number: 9673917
    Abstract: A method calibrates a spread spectrum receiver having a received signal strength below a noise floor. The method includes estimating an input noise power, and measuring a noise power output from the receiver. The method also includes comparing the estimated input noise power with the measured output noise power to determine at least one calibration value. The method further includes calibrating the receiver based upon the at least one calibration value.
    Type: Grant
    Filed: November 25, 2008
    Date of Patent: June 6, 2017
    Assignee: QUALCOMM Incorporated
    Inventors: Cormac S. Conroy, Leonid Sheynblat, Anup Savla, Roger Brockenbrough
  • Patent number: 9673802
    Abstract: Described are embodiments of stacked field effect transistor (FET) switch having a plurality of FET devices coupled in series to form an FET device stack. To prevent the FET device stack from being turned on during large signal conditions, one or more decoupling paths are provided and are configured to pass the time-variant input signal during the open state of the FET device stack. The first decoupling path may include a capacitor, a transistor, or the like, that passes the time-variant input signal by, for example, presenting a low impedance to the time-variant input signal during the open state. The decoupling paths may be connected so that the time-variant input signal bypasses a portion of the FET device stack during the open state.
    Type: Grant
    Filed: April 27, 2011
    Date of Patent: June 6, 2017
    Assignee: Qorvo US, Inc.
    Inventors: Marcus Granger-Jones, Christian Rye Iversen
  • Patent number: 9654095
    Abstract: A method is used to control an electronic device that includes a switching unit having a main MOS transistor having a substrate, a first conducting electrode and a second conducting electrode coupled to an output terminal. The method includes controlling the main transistor in such a way as to put it into an on state or an off state such that, when the main transistor is in the on state, the substrate and the first conducting electrode of the main transistor are connected to an input terminal and, when the main transistor is in the off state, the first conducting electrode of the main transistor is isolated from the input terminal and a first bias voltage is applied to the first conducting electrode and a second bias voltage is applied to the substrate of the main transistor.
    Type: Grant
    Filed: November 7, 2014
    Date of Patent: May 16, 2017
    Assignee: STMicroelectronics (Rousset) SAS
    Inventors: Bruno Gailhard, Michel Cuenca
  • Patent number: 9654057
    Abstract: In one aspect, a buffer circuit comprises a source or emitter follower input stage and output stage. A load is provided between the stages which comprises a representation of an output load of the buffer circuit. This improves the circuit linearity whilst enabling a high input impedance to be obtained. In another aspect, a buffer circuit comprises a source or emitter follower output stage. A load is in the form of a filter is provided and which comprises a representation of an output load of the buffer circuit.
    Type: Grant
    Filed: March 27, 2012
    Date of Patent: May 16, 2017
    Assignee: NXP, B.V.
    Inventors: Herve Marie, Lionel Guiraud
  • Patent number: 9634648
    Abstract: A circuit includes a divider circuit block configured to generate a trim term signal (VBG_TRIM) that is temperature and process independent. The circuit further includes a processing circuit block configured to multiply a temperature dependent reference voltage signal (TAP_GG) by a factor, and to sum the trim term signal with a result of the multiplication to generate an output reference voltage (VGG).
    Type: Grant
    Filed: December 5, 2013
    Date of Patent: April 25, 2017
    Assignee: XILINX, INC.
    Inventors: Shidong Zhou, Anil Kumar Kandala, Narendra Kumar Pulipati, Santosh Yachareni
  • Patent number: 9628068
    Abstract: Described are embodiments of stacked field effect transistor (FET) switch having a plurality of FET devices coupled in series to form an FET device stack. To prevent the FET device stack from being turned on during large signal conditions, one or more decoupling paths are provided and are configured to pass the time-variant input signal during the open state of the FET device stack. The first decoupling path may include a capacitor, a transistor, or the like, that passes the time-variant input signal by, for example, presenting a low impedance to the time-variant input signal during the open state. The decoupling paths may be connected so that the time-variant input signal bypasses a portion of the FET device stack during the open state.
    Type: Grant
    Filed: April 27, 2011
    Date of Patent: April 18, 2017
    Assignee: Qorvo US, Inc.
    Inventors: Marcus Granger-Jones, Christian Rye Iversen
  • Patent number: 9614575
    Abstract: A method and apparatus is disclosed to couple a transmission amplifier and a reception amplifier to a shared medium. An output of the transmission amplifier is directly coupled to an input of the reception amplifier to form a common connection. The transmission amplifier and the reception amplifier may receive a first amplifier bias via the common connection. In response to the first amplifier bias, the transmission amplifier provides a first communication signal to the shared medium and the reception amplifier does not provide a second communication signal from the shared medium. Alternatively, the transmission amplifier and the reception may receive a second amplifier bias via the common connection. In response to the second amplifier bias, the reception amplifier provides the second communication signal from the shared medium and the transmission amplifier does not provide the first communication signal to the shared medium.
    Type: Grant
    Filed: April 23, 2009
    Date of Patent: April 4, 2017
    Assignee: Avago Technologies General IP (Singapore) Pte. Ltd.
    Inventors: Ramon Gomez, Giuseppe Cusmai, Jianhong Xiao, Takayuki Hayashi, Young Shin
  • Patent number: 9601167
    Abstract: Disclosed are various embodiments related to dual-gate transistors and associated calibration circuitry. In one embodiment, dual-gate transistors may be configured in a sense amplifier arrangement, and calibration circuitry can be used to adjust an input offset of the sense amplifier. In another embodiment, a reference level voltage utilized in an amplifier with dual-gate transistors can be adjusted during a calibration sequence, and may be substantially unchanged from its nominal value outside of the calibration sequence. In another embodiment, a calibration sequence can be utilized to determine circuit results from a circuit including dual-gate transistors, and to adjust control gates to more closely coincide with expected or desired results. In yet another embodiment, a semiconductor memory device can include a memory array with amplifiers that include dual-gate transistors, as well as associated calibration circuitry.
    Type: Grant
    Filed: March 23, 2015
    Date of Patent: March 21, 2017
    Inventor: Michael C. Stephens, Jr.
  • Patent number: 9590617
    Abstract: A semiconductor device includes a high breakdown voltage, high Gm first transistor and a low breakdown voltage, low Gm second transistor connected in series between first and second nodes, and a low breakdown voltage, high Gm third transistor connected to the second transistor in parallel. When the second transistor is turned on, the first transistor turns on, and furthermore, when the third transistor is turned on, an electrically conducting state is established between the first and second nodes. The second, low breakdown voltage transistor is turned on to turn on the first, high breakdown voltage transistor, and a turn-on time with only limited variation can be achieved.
    Type: Grant
    Filed: April 5, 2012
    Date of Patent: March 7, 2017
    Assignee: SHARP KABUSHIKI KAISHA
    Inventors: Kenji Komiya, Shuji Wakaiki, Kohtaroh Kataoka, Masaru Nomura, Yoshiji Ohta, Hiroshi Iwata
  • Patent number: 9577629
    Abstract: Embodiments of the invention relate to a circuit for an active diode, a method for operating an active diode, and, based thereon, an integrated active diode system, a rectifier, and a system for voltage conversion and/or regulation, comprising at least one transistor by which a current defined as positive from a first connection to a second connection of the transistor can be controlled, and at least one measuring/control circuit (for determining the current by means of which the at least one transistor can be switched on for currents under and at most up to a predetermined, non-positive threshold value (i1<=ith<=0), and can otherwise be switched off.
    Type: Grant
    Filed: September 26, 2008
    Date of Patent: February 21, 2017
    Assignee: Infineon Technologies Austria AG
    Inventor: Gerald Deboy
  • Patent number: 9570974
    Abstract: A high-frequency switching circuit includes a high-frequency switching transistor, wherein a high-frequency signal-path extends via a channel-path of the high-frequency switching transistor. The high-frequency switching circuit includes a control circuit and the control circuit is configured to apply at least two different bias potentials to a substrate of the high-frequency switching transistor, depending on a control signal received by the control circuit.
    Type: Grant
    Filed: February 12, 2010
    Date of Patent: February 14, 2017
    Assignee: Infineon Technologies AG
    Inventors: Winfried Bakalski, Hans Taddiken, Nikolay Ilkov, Herbert Kebinger
  • Patent number: 9571092
    Abstract: Devices and circuits for high voltage switch (HVS) configurations. HVS may pass high voltage without suffering voltage drops. HVS may also guarantee safe operations for p-mos transistors. HVS may not sink current in its steady state. Further, HVS may select between two or more different voltage values to be passed onto the output node even after the high voltage has already been fully developed on the high voltage supply line.
    Type: Grant
    Filed: February 3, 2012
    Date of Patent: February 14, 2017
    Assignee: Longitude Semiconductor S.a.r.l.
    Inventors: Marco Passerini, Nicola Maglione
  • Patent number: 9559706
    Abstract: A phase interpolator circuit includes differential pairs of transistors, current source circuits, and a transimpedance amplifier circuit. Each of the current source circuits is coupled to provide current through one of the differential pairs of transistors. The transimpedance amplifier circuit converts the current through the differential pairs of transistors into a voltage signal.
    Type: Grant
    Filed: July 6, 2010
    Date of Patent: January 31, 2017
    Assignee: Altera Corporation
    Inventor: Wilfred Wee Kee King
  • Patent number: 9543928
    Abstract: A gate driving circuit and method can improve the tradeoff relation between the noise and the loss caused in the turn-OFF switching of semiconductor device. The gate driving circuit includes first and second series circuits. The first series circuit includes first and second MOSFETs connected in series. The gate terminal of the semiconductor device is connected to a negative potential side of the first MOSFET and a positive potential side of the second MOSFET. The emitter of the semiconductor device is connected to the negative potential side of the second MOSFET or a DC power source. The second series circuit includes a capacitor and a third MOSFET connected in series. The second series circuit is connected in parallel with the second MOSFET. The semiconductor device is turned OFF by turning ON the second and third MOSFETs and turning OFF the first MOSFET.
    Type: Grant
    Filed: August 11, 2008
    Date of Patent: January 10, 2017
    Assignee: FUJI ELECTRIC CO., LTD.
    Inventors: Keisuke Yamashiro, Hiromu Takubo
  • Patent number: 9543929
    Abstract: An power voltage generating unit for a radio frequency switch includes a first input and a second input respectively configured to receive a first control signal and a second control signal, wherein the first control signal and the second control signal are configured to control which one of a plurality of paths in the radio frequency switch is enabled, and at least one output, configured to output an auxiliary voltage, derived from at least one of the first control signal or the second control signal, that is used to operate the radio frequency switch. The power voltage may be a voltage used to power an inverting circuit used to enable a selected branch as an isolation branch or shunt branch.
    Type: Grant
    Filed: December 3, 2015
    Date of Patent: January 10, 2017
    Assignee: RichWave Technology Corp.
    Inventor: Chih-Sheng Chen
  • Patent number: 9491818
    Abstract: Disclosed is an LED driver adapted to an electronic transformer, where the LED driver can ensure that the electronic transformer meets minimum load current requirements, and operates during an entire AC period by clamping the minimum inductor current. By controlling the LED load current through a current stabilization control circuit, the LED load can operate with relatively high control accuracy and fast response speed. In addition, the LED driver can match various electronic transformers based on traditional circuit structures, and the LED load can operate without flicking.
    Type: Grant
    Filed: May 8, 2013
    Date of Patent: November 8, 2016
    Assignee: Silergy Semiconductor Technology (Hangzhou) LTD
    Inventors: Fenghong Fan, Qiukai Huang
  • Patent number: 9490810
    Abstract: AFE circuitry handles both voltage and current input signals. In one embodiment, both a voltage path and a current path are provided from the input. Switching circuitry selects one of the paths. A switch also turns on or off a current-to-voltage conversion circuit used to convert a current input into a voltage. In one embodiment, noise is significantly reduced by using a dedicated ground pin or terminal for the negative reference of a differential circuit. This applies the same external board noise, which is on the input signal, to the negative reference, so the noise is canceled in the differential signal. In one embodiment, temperature compensation is provided via an IPTAT circuit which is used to shift the voltage up in order to balance the decrease in DC voltage with increasing temperature.
    Type: Grant
    Filed: January 17, 2014
    Date of Patent: November 8, 2016
    Assignee: Marvell International Ltd.
    Inventors: Fu-Tai An, Yingxuan Li, Yonghua Song
  • Patent number: 9419836
    Abstract: In one exemplary embodiment, a method includes: inserting an indication of a cyclic prefix length into a transmission; and sending the transmission. In another exemplary embodiment, a method includes: receiving a transmission; and processing the received transmission to obtain an indication of a cyclic prefix length.
    Type: Grant
    Filed: April 21, 2009
    Date of Patent: August 16, 2016
    Assignee: Nokia Solutions and Networks Oy
    Inventors: Mieszko Chmiel, Przemyslaw Jan Czerepinski, Kaj Jansen