Abstract: The present invention includes an integrated system-on-chip device configured on a substrate member. The device has a data input/output interface provided on the substrate member and configured for a predefined data rate and protocol. The device has an input/output block provided on the substrate member and coupled to the data input/output interface. The input/output block comprises a SerDes block, a CDR block, a compensation block, and an equalizer block. The SerDes block is configured to convert a first data stream of N having a first predefined data rate at a first clock rate into a second data stream of M having a second predefined data rate at a second clock rate. The device has a driver module provided on the substrate member and coupled to a signal processing block, and a driver interface provided on the substrate member and coupled to the driver module and a silicon photonics device.

Abstract: An electronic device is provided. The electronic device includes a board, a first latch mechanism, and an expansion card. A controller is disposed on the board. The first latch mechanism is disposed on the board. The first latch mechanism is electrically connected to the controller. The expansion card is plugged in the first latch mechanism and disposed over the board. The expansion card is electrically connected to the controller through the first latch mechanism. The controller determines a connecting condition of the first latch mechanism according to a connecting signal provided by the expansion card.

Abstract: According to one embodiment, a controller of a memory system writes write data associated with a set of received write requests to a first write destination storage region in a first write mode of writing a plurality of bits per memory cell, without writing the write data to a second storage region. When receiving from a host a first request to cause a state of the first write destination storage region to transition to a second state in which writing is suspended, the controller transfers un-transferred remaining write data from a write buffer of the host to an internal buffer, and writes the remaining write data to the second storage region in a second write mode of writing 1 bit per memory cell.

Abstract: Systems and methods for processing commands at a random access memory. A series of commands are received to read data from the random access memory or to write data to the random access memory. The random access memory can process commands at a first rate when the series of commands matches a pattern, and at a second, slower, rate when the series of commands does not match the pattern. A determination is made as to whether the series of commands matches the pattern based on at least a current command and a prior command in the series of commands. A ready signal is asserted when said determining determines that the series of commands matches the pattern, where the random access memory is configured to receive and process commands faster than the second rate when the pattern is matched and the ready signal is asserted over a period of multiple commands.

Abstract: A semiconductor storage device and a control method thereof applicable to a plurality of different interface standards includes: a nonvolatile semiconductor memory, a first connector, a second connector, a determiner, and a controller. The first connector is provided to connect to an external apparatus with a first standard. The second connector is provided to connect to the external apparatus with a second standard. The determiner outputs a value according to a voltage value of a power supplied from the external apparatus via the first connector or the second connector. The controller controls communication executed between the external apparatus and the nonvolatile semiconductor memory via a connector according to the value output from the determiner among the first connector and the second connector.

Abstract: A data processing system includes a memory system including a memory device storing data and a controller performing a data program operation or a data read operation with the memory device, and a host suitable for requesting the data program operation or the data read operation from the memory system. The controller can perform a serial communication to control a memory which is arranged outside the memory system and engaged with the host.

Abstract: An operation circuit contains a parallel operation circuit including operators storage circuits. Each storage circuit has an input storage circuit that stores elements of an input vector in an order based on an index of each element; and a coefficient storage circuit including a ring buffer that stores elements of a row or column vector of a coefficient matrix in an order based on an index of each element. Each operator sequentially multiplies the elements of the coefficient matrix in the storage circuit by a corresponding one of the elements of the input vector, and adds a result of multiplication to a corresponding one of elements of the output vector based on the index thereof.

Abstract: A method includes obtaining a data, applying an erasure coding procedure to the data to obtain a plurality of data chunks and at least one parity chunk, deduplicating the plurality of data chunks to obtain a plurality of deduplicated data chunks, and storing, across a plurality of nodes, the plurality of deduplicated data chunks and the at least one parity chunk.

Abstract: Methods and apparatus are disclosed for securely erasing partitions of reconfigurable logic devices such as FPGAs in a multi-tenant server environment. In one example, a method of securely erasing an FPGA includes identifying one partition of previously-programmed resources in the FPGA, erasing the identified partition by storing new values in memory or storage elements of the identified partition, and storing new values in memory or storage elements of additional external resources electrically connected to the integrated circuit and associated with the identified partition. Thus, other partitions and subsequent users of the identified partition are prevented from accessing the securely erased data. A configuration circuit, accessible by a host computer via DMA, can be programmed into the FPGA reconfigurable logic for performing the disclosed erasing operations.

Abstract: Provided is a storage system that can store various types of and large amounts of sensor data while accurately compressing the sensor data without wasting storage resources. The storage system includes: a storage that records sensor data output from a plurality of sensors; a processor that controls recording of sensor data in the storage; and a memory that records parameters of the plurality of sensors. The processor reads parameters assigned to the sensors that output the sensor data from the memory, normalizes the sensor data based on the parameters, compresses the normalized sensor data, and records the compressed sensor data in the storage.

Abstract: In some examples, a system aggregates operational metric data of a plurality of storage volumes into aggregated operational metric data groups that correspond to different workload types of workloads for accessing data of a storage system. The system computes an operational metric for a first workload type of the different workload types, the operational metric relating to a resource of the storage system, where the computing of the operational metric for the first workload type comprises inputting aggregated operational metric data of a first aggregated operational metric data group of the aggregated operational metric data groups into a model trained at a system level of the storage system.

Abstract: An approach to identifying poorly performing data storage devices (DSDs) in a data storage system, such as hard disk drives (HDDs) and/or solid-state drives (SSDs), involves retrieving and evaluating a respective set of log pages, such as SCSI Log Sense counters, from each of multiple DSDs. Based on each respective set of log pages, a value for a Quality of Service (QoS) metric is determined for each respective DSD, where each QoS value represents an average percentage of bytes processed without the respective DSD performing an autonomous error correction. In response to a particular DSD reaching a predetermined threshold QoS value, an in-situ repair may be determined for the particular DSD or the particular DSD may be added to a list of candidate DSDs for further examination, which may include an FRPH examination for suitably configured DSDs.

Abstract: A method of controlling discard operations is performed in a system that includes a host device and a data storage device. The method includes providing a shared discard bitmap accessed commonly by the host device and data storage device. The shared discard bitmap includes discard bits in one-to-one correspondence with target sectors of a nonvolatile memory device in the data storage device. The method also includes setting bit values of the discard bits stored in the shared discard bitmap, the bit values indicating whether data stored in each of the target sectors are discardable. An asynchronous discard operation may then be performed with respect to the target sectors based on the bit values of the discard bits stored in the shared discard bitmap.

Abstract: An interface bridge to enable communication between a first integrated circuit die and a second integrated circuit die is disclosed. The two integrated circuit die may be connected via chip-to-chip interconnects. The first integrated circuit die may include programmable logic fabric. The second integrated circuit die may support the first integrated circuit die. The first integrated circuit die and the secondary integrated circuit die may communicate with one another via the chip-to-chip interconnects using an interface bridge. The first and second component integrated circuits may include circuitry to implement the interface bridge, which may provide source-synchronous communication using a data receive clock from the second integrated circuit die to the first integrated circuit die.

Abstract: A method for error management in bus communication is disclosed. A first bus subscriber generates a first bus message and writes a bus error code into a bus data area of a first bus message. The second bus subscriber identifies the error by evaluating the bus error code. The first bus subscriber stores an error identification of the error, generates a first bus message and writes the bus error code into the bus data area of the first bus message. A second bus message with a request for transmission of the error identification is generated by the second bus subscriber. A third bus message is generated by the first bus subscriber and the stored error identification is written into the bus data area of the third bus message. The second bus subscriber identifies the errors by evaluating the bus error code and the error identification.

Abstract: A method, a hardware accelerator, and a system for performing computational storage utilizing a hardware accelerator device that includes a dedicated buffer memory residing on the hardware accelerator device and is connected to a central processing unit (CPU) via a bus includes receiving, at the hardware accelerator device, computation data from the CPU computing device via the bus, performing, at the hardware accelerator device, a check pointing operation on the received computation data to generate check point data, storing the generated check point data on the dedicated buffer memory residing on the hardware accelerator device, and transmitting the check point data directly from the dedicated buffer memory to a solid state memory connected to the hardware accelerator device via the bus for storage, wherein transmitting the check point data bypasses the CPU.

Abstract: A multichip package having a main die coupled to one or more daughter dies is provided. The main die may include embedded universal interface blocks (UIB) each of which can be used to interface with a corresponding daughter die to support high bandwidth parallel or serial communications. Each UIB may include an integrated processor subsystem and associated pattern sequencing logic to perform interface initialization and margining operations. Each UIB may perform simultaneous accesses to a daughter die across one or more channels. Each UIB may also include multiple phase-locked loop circuits for providing different clock signals to different portions of the UIB and a 2× clock phase generation logic. Each UIB may include multiple IO modules, each of which may optionally include its own duty cycle correction circuit. Each IO module may include buffer circuits, each of which may have a de-emphasis control logic for adjusting buffer drive strength.

Abstract: A server box embodiment is disclosed that generally comprises an array of dummy HDDs that share a common set of universal disk drive components in a master components module, or power module. Each dummy HDDs is constructed without expensive onboard chipsets that control the normal functionality of a standard HDD. By sharing expensive chipsets in a master components module (power module) money can be saved in building and selling the dummy HDD server. Embodiments envision a power module possessing the needed chipset functionality that is missing in a dummy HDD. The power module can be made to move from dummy HDD to dummy HDD supplying the necessary chipset in a shared manner when data is being stored or retrieved for client or end-user.

Abstract: A nonvolatile memory device includes a memory cell array including first to fourth planes, a page buffer circuit that includes first to fourth page buffer units connected with the first to fourth planes, respectively, an input/output circuit that includes a first input/output unit connected with the first to fourth page buffer units and a second input/output unit connected with the second and fourth page buffer units, and control logic that controls the input/output circuit to output first data from one of the first to fourth page buffer units through the first input/output unit in a first read mode and output second data from one of the first and third page buffer units through the first input/output unit and third data from one of the second and fourth page buffer units through the second input/output unit in a second read mode.

Abstract: Examples include techniques for managing high priority (HP) and low priority (LP) write transaction requests by a storage device. An embodiment includes receiving, at a storage controller for a storage device, a write transaction request from a requestor to write data to one or more memory devices in the storage device. When the write transaction request is for a high priority (HP) write, coalescing the write data into a transaction buffer in a memory of the storage device, sending an acknowledgment for the write transaction request to the requestor, and writing the write data into the one or more memory devices. When the write transaction request is for a low priority (LP) write, writing the write data into the one or more memory devices, and then sending an acknowledgment for the write transaction request to the requestor.