Abstract: An apparatus including a memory structure comprising non-volatile memory cells and a microcontroller. The microcontroller is configured to output Core-Timing-Control (CTC) signals. The CTC signals are used to control voltages that are applied in the memory structure. For example, CTC signals may be used to control the timing of voltages applied to word lines, bit lines, select lines, and other elements or control lines in the memory core. The microcontroller is configured to output CTC signals having many different variations under various modes/parameter conditions. The apparatus may include storage containing reaction data according to dynamic conditions. The microcontroller may be configured to lookup or compute the CTC signals based on the dynamic conditions and the reaction data. Various data storage formats are disclosed, which can be used to efficiently store many varieties of data with minimum usage of memory.

Abstract: Examples include distribution of I/O Q-connections of an NVMe™ subsystem among hosts that are to communicate with the NVMe™ subsystem in an NVMe™ zone of a system. Some examples receive information including a number of I/O Q-connections available at the NVMe™ subsystem, register the number of available I/O Q-connections of the NVMe™ subsystem with an NVMe™ fabric controller, determine a number of I/O Q-connections of the NVMe™ subsystem allowed to be used by each host and send to, each host, a first notification including the number of allowed I/O Q-connections of the NVMe™ subsystem to be used by the host.

Abstract: A nonvolatile memory device includes a memory cell array including first to fourth planes, a page buffer circuit that includes first to fourth page buffer units connected with the first to fourth planes, respectively, an input/output circuit that includes a first input/output unit connected with the first to fourth page buffer units and a second input/output unit connected with the second and fourth page buffer units, and control logic that controls the input/output circuit to output first data from one of the first to fourth page buffer units through the first input/output unit in a first read mode and output second data from one of the first and third page buffer units through the first input/output unit and third data from one of the second and fourth page buffer units through the second input/output unit in a second read mode.

Abstract: Provided are a computer program product, system, and method for using insertion points to determine locations in a cache list at which to move processed tracks. There are a plurality of insertion points to a cache list for the cache having a least recently used (LRU) end and a most recently used (MRU) end, wherein each insertion point of the insertion points identifies a track in the cache list. An insertion point of the insertion points is determined at which to move the processed track in response to determining that a processed track is indicated to move to the MRU end. The processed track is indicated at a position in the cache list with respect to the determined insertion point.

Abstract: A resistive memory including a storage array, a storage circuit, a control circuit, a voltage generation circuit and an access circuit is provided. The storage array includes a plurality of blocks. Each block includes a plurality of memory cells. The storage circuit stores a plurality of count values. Each of the count values indicates the number of times that a corresponding block performs a write operation. The control circuit generates a control signal according to the count values when an external command is a write command. The voltage generation circuit provides an operation voltage group according to the control signal. The access circuit accesses the storage array according to the operation voltage group.

Abstract: A real-time computational device includes a programmable real-time processor, a communications input port which is connected to the programmable real-time processor through a first broadside interface, and a communications output port which is connected to the programmable real-time processor through a second broadside interface. Both broadside interfaces enable 1024 bits of data to be transferred across each of the broadside interfaces in a single clock cycle of the programmable real-time processor.

Abstract: A system and method are described for configuring a motherboard using expansion cards plugged into motherboard slots. In particular, each of the expansion cards can include a control signal that is supplied to the motherboard and that can configure hardware positioned on the motherboard. In one embodiment, the configuration allows a communication path to be switched on to allow the expansion cards to cross communicate.

Abstract: Systems and methods for asynchronous mapping of a hot-plugged I/O device associated with a virtual machine. An example method comprises: executing, by a host computer system, a virtual machine managed by a hypervisor, wherein the virtual machine is associated with a hot-pluggable input/output (I/O) device; responsive to detecting removal of the I/O device, unpin a memory buffer associated with the I/O device; and responsive to receiving a signal indicating completion of unpinning the memory buffer, release the I/O device from the hypervisor.

Abstract: A method for sending data, from an upstream device to a downstream device, including sending a piece of data from one among a plurality of virtual channels sharing the same input buffer memory of the downstream device, if this virtual channel uses a number of memory locations of the input buffer memory strictly less than a current ceiling. It further comprises measuring a communication latency between the upstream and downstream devices, and calculating the current ceiling from the measured latency.

Abstract: A storage system is coupled to another storage system and a higher-level apparatus via a network, and copies write data received from the higher-level apparatus to the other storage system. This storage system is provided with interface units, each provided with a plurality of ports that can be coupled to the network; and a plurality of controllers coupled to a respective one of the interface units. Each controller has a processor unit. When each processor unit receives write data from the higher-level apparatus via a first port coupled to the interface unit that is coupled to the controller to which the processor unit belongs, the processor unit selects, from among the ports of the interface unit coupled to the controller to which the processor unit belongs, a second port for transmitting the write data to the other storage system, and transmits the write data to the other storage system.

Abstract: Method and apparatus for managing data in a non-volatile memory (NVM) of a storage device, such as a solid-state drive (SSD). An initial temperature is stored associated with the programming of data to memory cells in the NVM. A current temperature associated with the NVM is subsequently measured. At such time that a difference interval between the initial and current temperatures exceeds a selected threshold, a preemptive parametric adjustment operation is applied to the NVM. The operation may include a read voltage calibration, a read voltage increment adjustment, and/or a forced garbage collection operation. The operation results in a new set of read voltage set points for the data suitable for the current temperature, and is carried out independently of any pending read commands associated with the data. The initial temperature can be measured during the programming of the data, or measured during the most recent read voltage calibration operation.

Abstract: An arithmetic processing device includes circuitry configured to add an identifier of a request source that generates a prefetch request into the prefetch request, and output, in response to detecting a certain number of cache hits less than a first threshold, each of the cache hits occurring in a first cache memory provided at a lower hierarchical level than a second cache memory by each prefetch request into which a first identifier is added, a notification for suppressing a prefetch request issued for the lower hierarchical level of the first cache memory from a first request source identified by the first identifier.

Abstract: A storage and communication apparatus for plugging into a server, includes a circuit board, a bus interface, a Medium Access Control (MAC) processor, one or more storage devices and at least one Central Processing Unit (CPU). The bus interface is configured to connect the apparatus at least to a processor of the server. The MAC is mounted on the circuit board and is configured to connect to a communication network. The storage devices are mounted on the circuit board and are configured to store data. The CPU is mounted on the circuit board and is configured to expose the storage devices both (i) to the processor of the server via the bus interface, and (ii) indirectly to other servers over the communication network.

Abstract: Applying a rate limit across a plurality of storage systems, including: determining a rate limit for paired storage systems; receiving, by a first storage system, an amount of I/O operations serviced by the second storage system during a previous predetermined period of time; determining whether the amount of I/O operations serviced by the second storage system is less than half of the rate limit for the paired storage systems; if so, setting local a rate limit for a next predetermined period of time for the first storage system to the difference between the rate limit for the paired storage systems and the amount of I/O operations serviced by the second storage system during the previous predetermined period of time; and otherwise, setting a local rate limit for a next predetermined period of time for the first storage system to half of the rate limit for the paired storage systems.

Abstract: Aspects of the present disclosure involve a system and method for performing operations comprising providing to a client device, a messaging application comprising multiple features; accessing a configuration rule that associates a device property rule with a feature; determining at a first point in time, that a property of the client device matches the device property rule associated with the configuration rule; in response to determining that the property of the client device matches the device property rule associated with the configuration rule, enabling the feature on the client device at the first point in time; receiving an updated property of the client device at a second point in time; and in response to determining that the updated property of the client device fails to match the device property rule associated with the configuration rule at the second point in time, disabling the feature on the client device.

Abstract: In some examples, a logic device may be connected to: (i) a ThunderBolt (TBT) output of a CPU that lacks a DisplayPort (DP) input and (ii) a DP output of a GPU. The logic device may determine a presence of a video signal, e.g., either: (1) TBT video from the CPU or (2) DP video from the GPU. The logic device may re-time the video signal to create re-timed video and output the re-timed video using a USB-C port. If the logic device determines that the video signal is DP, then the logic device may select a DisplayPort Alternate Mode of the USB-C port and output the re-timed video signal using four differential pairs of the USB-C port. If the logic device determines that the video signal is TBT, then the logic device may output the re-timed video signal using two differential pairs of the USB-C port.

Abstract: A driver associated with a host peripheral component interconnect (PCI) device may be initiated, the host PCI device to be accessed by an application executed by a guest operating system (OS) of a guest using user space memory of the guest. A host page table switching instruction may be executed using the driver to cause a switch from a first host page table structure to a second host page table structure. The host PCI device may be accessed using the driver via a PCI alias address that is mapped to a host PCI address in the second host page table structure. Application code associated with the application may be prevented from accessing a host memory address in the second host page table structure.

Abstract: An approach to identifying problematic data storage devices, such as hard disk drives (HDDs), in a data storage system involves retrieving and evaluating a respective recovery log, such as a media error section of a device status log, from each of multiple HDDs. Based on each recovery log, a value for a Full Recoveries Per Hour (FRPH) metric is determined for each read-write head of each respective HDD. Generally, the FRPH metric characterizes the amount of time a head has spent performing recovery operations. In response to a particular head FRPH reaching a pre-determined threshold value, an in-situ repair can be determined for the HDD in which the head operates. Similarly, in the context of solid-state drives (SSDs), a latency metric is determinable based on time spent waiting on resolving input/output (IO) request collisions, on which an in-situ repair can be based.

Abstract: A computational system includes one or more processors. Each processor has multiple registers, as well attached memory to hold instructions. The processor is coupled to one or more broadside interfaces. A broadside interface allows the processor to load or store an entire widget state in a single clock cycle of the processor. The broadside interface also allows the processor to move and store 32 bytes of information into RAM in less than four to five clock cycles of the processor while the processor concurrently performs one or more mathematical operations on the information while the move and store operation is taking place.

Abstract: A memory-adaptive processing method for a convolutional neural network includes a feature map counting step, a size relation counting step and a convolution calculating step. The feature map counting step is for counting a plurality of input channels of an input feature map tile and a plurality of output channels of an output feature map tile for a convolutional layer operation of the convolutional neural network. The size relation counting step is for obtaining a cache free space size in a feature map cache and counting a size relation among a total input size, a total output size and the cache free space size of the feature map cache. The convolution calculating step is for performing the convolutional layer operation according to a memory-adaptive processing technique.