Abstract: A system for monitoring inter-integrated circuit (I2C) communication includes a power supply, a battery backup unit, an I2C serial clock line (SCL) coupled between the power supply and the battery backup unit, an I2C serial data line (SDA) coupled between the power supply and the battery backup unit, and a controller. A first monitor line is coupled between the controller and the I2C serial clock line, and a second monitor line is coupled between the controller and the I2C serial data line. The controller is configured to monitor a digital communication transmitted on the I2C serial clock and data lines between the power supply and the battery backup unit, interpret a message included in the monitored digital communication, and perform a control function according to the interpreted message.

Abstract: A method, system, and apparatus are provided for a configurable streaming operator to join or aggregate input data streams in a streaming application topology. The configurable operator may include a configuration data stream that allows for the selection of a varying number of input streams to join or aggregate. Introducing the configuration stream into a streaming operator allows the underlying operator to selectively use the remaining input streams based on the configuration stream as well as influencing the resulting output stream as defined by the configuration stream to provide flexibility in handling various configurations with a minimum and/or maximum of input streams.

Abstract: A computer-implemented method, according to one embodiment, includes: receiving an I/O queue creation request, and identifying a first CPU core that can satisfy the I/O queue creation request. A determination is made as to whether the first CPU core already has an I/O queue formed thereon. In response to determining that the first CPU core already has an I/O queue formed thereon, a determination is made as to whether any CPU cores do not already have an I/O queue formed thereon. In response to determining that each CPU core already has an I/O queue formed thereon, the host is informed that satisfying the I/O queue creation request will cause an overlap with existing I/O queues. In response to receiving an indication from the host to satisfy the I/O queue creation request despite the overlap, instructions are sent to use the first CPU core to satisfy the I/O queue creation request.

Abstract: A multichip package having a main die coupled to one or more daughter dies is provided. The main die may include embedded universal interface blocks (UIB) each of which can be used to interface with a corresponding daughter die to support high bandwidth parallel or serial communications. Each UIB may include an integrated processor subsystem and associated pattern sequencing logic to perform interface initialization and margining operations. Each UIB may perform simultaneous accesses to a daughter die across one or more channels. Each UIB may also include multiple phase-locked loop circuits for providing different clock signals to different portions of the UIB and a 2× clock phase generation logic. Each UIB may include multiple IO modules, each of which may optionally include its own duty cycle correction circuit. Each IO module may include buffer circuits, each of which may have a de-emphasis control logic for adjusting buffer drive strength.

Abstract: In one embodiment, a method includes establishing a connection between a hardware switch and a console port, connecting the console port to a first central processing unit (CPU) using the hardware switch, and receiving, from the console port, a first character stream. The method also includes detecting, by the hardware switch, a first special character within the first character stream. The method further includes connecting, by the hardware switch, the console port to a second CPU in response to detecting the first special character within the first character stream.

Abstract: The disclosure provides for a reactive cache coherence protocol that has efficiencies over proactive approaches. Rather than proactively performing remediation when a data item is invalidated, a destination endpoint checks cache coherence upon receiving an indication of a cache hit, and based at least on detecting a lack of coherence, performs a reactive remediation process. For example, the incoherence may be fixed by replacing, as a cached data item, a data block indicated by the cache hit with a replacement data block that triggered the cache hit.

Abstract: An indication can be received that a host system is to become idle for a period of time. A background operation can be selected from multiple background operations based on the period of time that the host system is to become idle. The selected background operation can be executed during the period of time that the host system is to become idle.

Abstract: A data processing method and system, where the method includes: receiving, by a non-volatile memory express (NVMe) controller, a first Peripheral Component Interconnect express (PCIe) packet sent by a host, where a memory in the NVMe controller is provided with at least one input/output (I/O) submission queue, and the first PCIe packet includes entrance information of a target I/O submission queue and at least one submission queue entry (SQE); and storing the at least one SQE in the target I/O submission queue based on the entrance information of the target I/O submission queue. Therefore, an NVMe data processing process is simplified and less time-consuming, and data processing efficiency is improved.

Abstract: Systems, methods, and apparatuses relating to circuitry to implement individually revocable capabilities for enforcing temporal memory safety are described. In one embodiment, a hardware processor comprises an execution unit to execute an instruction to request access to a block of memory through a pointer to the block of memory, and a memory controller circuit to allow access to the block of memory when an allocated object tag in the pointer is validated with an allocated object tag in an entry of a capability table in memory that is indexed by an index value in the pointer, wherein the memory controller circuit is to clear the allocated object tag in the capability table when a corresponding object is deallocated.

Abstract: A multichip package having a main die coupled to one or more daughter dies is provided. The main die may include embedded universal interface blocks (UIB) each of which can be used to interface with a corresponding daughter die to support high bandwidth parallel or serial communications. Each UIB may include an integrated processor subsystem and associated pattern sequencing logic to perform interface initialization and margining operations. Each UIB may perform simultaneous accesses to a daughter die across one or more channels. Each UIB may also include multiple phase-locked loop circuits for providing different clock signals to different portions of the UIB and a 2× clock phase generation logic. Each UIB may include multiple IO modules, each of which may optionally include its own duty cycle correction circuit. Each IO module may include buffer circuits, each of which may have a de-emphasis control logic for adjusting buffer drive strength.

Abstract: A cable may be satisfactorily used that has a specific function such as a register that holds specification data and a current consumption unit such as an element for adjusting signal quality. The cable is connected between a first electronic device and a second electronic device. A determination unit determines whether or not the first electronic device is a compatible electronic device. A control unit performs control to operate in a compatible mode when the first electronic device is a compatible electronic device and operate in a non-compatible mode when the first electronic device is not a compatible electronic device on the basis of the determination result by the determination unit. Furthermore, an electronic device is connected to an external device via the cable. The determination unit determines whether or not the cable is a compatible cable.

Abstract: A method for dispatching input-output in a system. The system may include a centralized processing circuit, a plurality of persistent storage targets, a first input-output processor, and a second input-output processor. The method may include determining whether the first input-output processor is connected to a first target of the plurality of persistent storage targets; determining whether the second input-output processor is connected to the first target; and in response to determining that both the first input-output processor is connected to the first target, and the second input-output processor is connected to the first target, dispatching a first plurality of input-output requests, each to either the first input-output processor or the second input-output processor, the dispatching being in proportion to a service rate of the first input-output processor to the first target and a service rate of the second input-output processor to the first target, respectively.

Abstract: Provided is a storage system in which a plurality of storage controllers communicate with each other and an identifier of each storage controller is determined. The storage system includes a plurality of controllers that receive and process an input and output request specifying any of a plurality of volumes from an external device, and a plurality of switches each having a plurality of ports. The plurality of controllers are connected in parallel to the plurality of switches and communicate with each other via the plurality of switches. Each of the plurality of controllers acquires a plurality of port identifiers identifying a plurality of connected ports from the connected switches, and determines a controller identifier in the storage system based on the acquired plurality of port identifiers.

Abstract: A data conversion control apparatus, comprising: at least one first interface each for coupling a first external interface, both of the first interface and the first external interface being in accordance with a predetermined physical interface standard, wherein data transmitted between the first interface and the first external interface is in accordance with a configurable application layer protocol; at least one second interface each for coupling a second external interface, wherein the second external interface is a memory interface in accordance with a predetermined memory interface standard, and the second interface is configurable to match the predetermined memory interface standard; and a data rebuild unit coupled between the at least one first interface and the at least one second interface, wherein the data rebuild unit is configured to rebuild data such that data can be transmitted in respective formats between the at least one first interface and the at least one second interface.

Abstract: A processing device determines a set of difference error counts corresponding to multiple programming distributions of a memory sub-system. A valley having a lowest valley margin is identified based on a comparison of the set of difference error counts. Based on the set of difference error counts, a program targeting rule from a set of rules. A program targeting operation is performed, based on the program targeting rule, a program targeting operation to adjust a voltage associated with an erase distribution of the memory sub-system.

Abstract: A server box embodiment is disclosed that generally comprises an array of dummy HDDs that share a common set of universal disk drive components in a master components module, or power module. Each dummy HDDs is constructed without expensive onboard chipsets that control the normal functionality of a standard HDD. By sharing expensive chipsets in a master components module (power module) money can be saved in building and selling the dummy HDD server. Embodiments envision a power module possessing the needed chipset functionality that is missing in a dummy HDD. The power module can be made to move from dummy HDD to dummy HDD supplying the necessary chipset in a shared manner when data is being stored or retrieved for client or end-user.

Abstract: An apparatus comprises a host device configured to communicate over a network with first and second storage systems. The host device detects an association in at least one of the first and second storage systems between a source logical storage device of the first storage system and a target logical storage device of the second storage system, and responsive to the detected association, establishes a migration session in the host device for migration of the source logical storage device to the target logical storage device. The host device also obtains an indication from at least one of the first and second storage systems that a corresponding migration session has been activated in the first and second storage systems, and activates the previously-established migration session in the host device based at least in part on the obtained indication for migration of the source logical storage device to the target logical storage device.

Abstract: Method and apparatus are disclosed for cache control in a parallel processing system. The apparatus includes a plurality of application specific engines configured to generate a plurality of commands, a cache array configured to store the plurality of commands, and a cache command controller configured to receive a command asynchronously from an application specific engine in the plurality of application specific engines, update the cache array to include the received command, and validate the updated cache array while maintaining parallel accessing of the cache array by the plurality of application specific engines.

Abstract: An interface bridge to enable communication between a first integrated circuit die and a second integrated circuit die is disclosed. The two integrated circuit die may be connected via chip-to-chip interconnects. The first integrated circuit die may include programmable logic fabric. The second integrated circuit die may support the first integrated circuit die. The first integrated circuit die and the secondary integrated circuit die may communicate with one another via the chip-to-chip interconnects using an interface bridge. The first and second component integrated circuits may include circuitry to implement the interface bridge, which may provide source-synchronous communication using a data receive clock from the second integrated circuit die to the first integrated circuit die.

Abstract: A method may include selectively instantiating a bridge conductor component at a first printed circuit board (PCB) pad and a second PCB pad to provide a first universal serial bus (USB) receptacle configuration at an information handling system, the first configuration having a USB type-C receptacle at a first location at the PCB. The method may further include selectively instantiating the bridge conductor component at the first PCB pad and a third PCB pad to provide a second USB receptacle configuration at an information handling system, the second configuration having a USB type-A receptacle at the first location at the PCB. Instantiation of the bridge conductor component at the first and the second PCB pads is mutually exclusive to instantiation of the first bridge conductor component at the first and the third PCB pads.