Abstract: A server box embodiment is disclosed that generally comprises an array of dummy HDDs that share a common set of universal disk drive components in a master components module, or power module. Each dummy HDDs is constructed without expensive onboard chipsets that control the normal functionality of a standard HDD. By sharing expensive chipsets in a master components module (power module) money can be saved in building and selling the dummy HDD server. Embodiments envision a power module possessing the needed chipset functionality that is missing in a dummy HDD. The power module can be made to move from dummy HDD to dummy HDD supplying the necessary chipset in a shared manner when data is being stored or retrieved for client or end-user.

Abstract: A data writing method, a memory controlling circuit unit and a memory storage device are provided. The method includes: receiving a plurality of data; writing the plurality of data into a first physical erasing unit by using a multi-page programming mode; and writing at least one first data of the plurality of data into a second physical erasing unit by using a single-page programming mode; verifying the plurality of data stored in the first physical erasing unit; and if the verification fails, performing a writing operation to a third physical erasing unit by using the multi-page programming mode according to the at least one first data and the plurality of data.

Abstract: Storage-based slow drain detecting and automated resolution is provided herein. A data storage system as described herein can include a memory that stores computer executable components and a processor that executes computer executable components stored in the memory. The computer executable components can include a switch query component that obtains a host transfer rate negotiated between a host device and a network switch from a host-connected port of the network switch; a comparison component that compares the host transfer rate to an array transfer rate negotiated between the network switch and a storage array; and a rate limiter component that limits a data transfer from the storage array to the host device to the host transfer rate in response to the host transfer rate being less than the array transfer rate.

Abstract: A drive and control system for a lawn tractor includes a CAN-Bus network, a vehicle controller, a pair of hydrostatic or electric transaxles controlled by respective electronic drive controllers, and one or more steering and drive input devices coupled to respective sensor(s) for sensing user steering and drive inputs. The vehicle controller communicates with one or more vehicle sensors and one or more vehicle controllers that control one or more vehicle components via the CAN-Bus network. The vehicle controller processes the user's steering and drive inputs and posts on the CAN-Bus network digital drive signals configured to obtain the desired speed and direction of motion of the lawn tractor. The electronic drive controllers convert the digital drive signals to appropriate signals for driving the hydrostatic transaxles or the electric transaxles, as equipped, based on tunable motion parameters to obtain the desired speed and direction of motion of the lawn tractor.

Abstract: A drive and control system for a lawn tractor includes one or more sensors configured to detect an operational parameter of an aspect of the vehicle, and one or more controllers for controlling one or more components of the vehicle and for receiving data output from the one or more sensors. The controller communicates with the one or more sensors and one or more vehicle modules configured to control one or more vehicle components via a CAN Bus network. The controller may be coupled to an IMU mounted on the vehicle for dynamically controlling the vehicle on sloped terrain, for example. The controller may be accessible from a remote device over a wireless network for communicating setup, diagnostic, and performance data to and from the vehicle.

Abstract: A drive and control system for a lawn tractor includes a CAN-Bus network, a vehicle controller, a pair of hydrostatic or electric transaxles controlled by respective electronic drive controllers, and one or more steering and drive input devices coupled to respective sensor(s) for sensing user steering and drive inputs. The vehicle controller communicates with one or more vehicle sensors and one or more vehicle controllers that control one or more vehicle components via the CAN-Bus network. The vehicle controller processes the user's steering and drive inputs and posts on the CAN-Bus network digital drive signals configured to obtain the desired speed and direction of motion of the lawn tractor. The electronic drive controllers convert the digital drive signals to appropriate signals for driving the hydrostatic transaxles or the electric transaxles, as equipped, based on tunable motion parameters to obtain the desired speed and direction of motion of the lawn tractor.

Abstract: According to some example embodiments according to the present disclosure, a device includes a printed circuit board (PCB); a solid state drive (SSD) connected at a first side of the PCB via at least one SSD connector; at least one field programmable gate array (FPGA) attached to the PCB at a second side of the PCB; and at least one front end connector attached to the PCB at a third side of the PCB, wherein the device is configured to process data stored in the SSD based on a command received via the at least one front end connector.

Abstract: A circuit for asynchronous data transfer includes a slave device having an asynchronous slave clock for transferring data to a master device having a master clock. The slave clock is a non-continuous clock signal. The slave device includes a clock detection circuit, a register bank, a temporary storage register, and a datapath selector. The slave device receives a data transfer command from the master device. The clock detection circuit detects a presence of the slave clock signal and generates a sync signal. To transfer the data to the master device, the datapath selector selects one of the temporary storage register and the register bank based on the sync signal. The slave device ensures seamless data transfer to the master device regardless of the presence or absence of the slave clock signal.

Abstract: To increase the speed with which a Second Layer Address Table (SLAT) is traversed, memory having the same access permissions is contiguously arranged such that one or more hierarchical levels of the SLAT need not be referenced, thereby resulting in more efficient SLAT traversal. “Slabs” of memory are established whose memory range is sufficiently large that reference to a hierarchically lower level table can be skipped and a hierarchically higher level table's entries can directly identify relevant memory addresses. Such slabs are aligned to avoid smaller intermediate memory ranges. The loading of code or data into memory is performed based on a next available memory location within a slab having equivalent access permissions, or, if such a slab is not available, or if an existing slab does not have a sufficient quantity of available memory remaining, a new slab with the proper access permissions is established.

Abstract: Methods and devices for synchronizing audio among a plurality of display devices in communication with a computer device may include determining a plurality of audio data subsets with audio data from an audio stream to transmit to a plurality of display devices in communication with the computer device via a universal serial bus (USB) connection. The methods and devices may include obtaining a current frame number of a display device render buffer from a first display device of the plurality of display devices. The methods and devices may include determining an updated frame number by adding a constant to the current frame number; and generating a plurality of USB request blocks with the updated frame number and packets with the plurality of audio data subsets. The methods and devices may include sending the USB request blocks to a corresponding display device of the plurality of display devices.

Abstract: A data processing system includes a memory system including a memory device storing data and a controller performing a data program operation or a data read operation with the memory device, and a host suitable for requesting the data program operation or the data read operation from the memory system. The controller can perform a serial communication to control a memory which is arranged outside the memory system and engaged with the host.

Abstract: A method and memory apparatus that operate to minimize and limit memory initialization time when powering up after an unexpected shutdown. Instead of relying only on a cached log table that is lost when memory powers down unexpectedly, the method and apparatus disclosed herein preserve the information needed to rebuild the log table within predefined memory locations. These predefined locations are optimized such that parallel sensing will capture initialization information for a certain number of word lines across all dies and planes within the memory structure during a single read operation at power up.

Abstract: A multichip package may include at least a main die mounted on a substrate. The main die may be coupled to one or more transceiver dies also mounted on the substrate. The main die may include one or more universal interface blocks configured to interface with an on-package memory device or an on-package expansion die, both of which can be mounted on the substrate. The expansion die may include external memory interface (EMIF) components for communicating with off-package memory devices and/or bulk random-access memory (RAM) components for storing large amounts of data for the main die. Smaller input-output blocks such as GPIO (general purpose input-output) or LVDS (low-voltage differential signaling) interfaces may be formed within the core fabric of the main die without causing routing congestion while providing the necessary clock source.

Abstract: Systems and methods for processing commands at a random access memory. A series of commands are received to read data from the random access memory or to write data to the random access memory. The random access memory can process commands at a first rate when the series of commands matches a pattern, and at a second, slower, rate when the series of commands does not match the pattern. A determination is made as to whether the series of commands matches the pattern based on at least a current command and a prior command in the series of commands. A ready signal is asserted when said determining determines that the series of commands matches the pattern, where the random access memory is configured to receive and process commands faster than the second rate when the pattern is matched and the ready signal is asserted over a period of multiple commands.

Abstract: A method for increasing compatibility of DisplayPort includes: providing a first source device, a second source device, a controller, and a sink device, wherein the first source device is connected to the controller; the first source device transmitting a first image signal to the sink device via a main link for displaying the first image signal on the sink device; causing the controller to disconnect from the first source device and connect to the second source device; executing a simulation process to generate a DC level variation on an auxiliary channel between the controller and the sink device; the second source device transmitting auxiliary data to the sink device; the sink device transmitting link data back to the second source device; and the second source device transmitting a second image signal to the sink device via a second main link for displaying the second image signal on the sink device.

Abstract: A storage control device, includes: a memory configured to store meta information and map information, the meta information associates a logical address to identify data from an information processing device which uses a storage with a data block identifier to identify a data block used for an arrangement of the data on the storage and including a header area and a payload area and an index indicating an order of additional writing of the data, the map information associates the data block identifier with a physical identifier indicating a physical position on the storage; and a processor specifies the data block and a write position in a payload area based on the physical identifier and the index, writes the data in the specified data block and performs a write control to write a data unit header including an offset and a data length at a position designated by the index.

Abstract: The present invention includes an integrated system-on-chip device configured on a substrate member. The device has a data input/output interface provided on the substrate member and configured for a predefined data rate and protocol. The device has an input/output block provided on the substrate member and coupled to the data input/output interface. The input/output block comprises a SerDes block, a CDR block, a compensation block, and an equalizer block. The SerDes block is configured to convert a first data stream of N having a first predefined data rate at a first clock rate into a second data stream of M having a second predefined data rate at a second clock rate. The device has a driver module provided on the substrate member and coupled to a signal processing block, and a driver interface provided on the substrate member and coupled to the driver module and a silicon photonics device.

Abstract: A NVMe™ or NVMe-over-fabrics enabled device with video codec functionality may be seen to overcome scalability problem of known hardware assisted video codec solutions. The device of aspects of the present application may or may not have storage media. A host computer communicates with the device through NVMe™ commands. The device may be in one of many SSD form factors, such as U.2 or AIC. The device may be provided as a component in NVMe-enabled computers or NVMe-over-fabrics-enabled systems.

Abstract: Provided is an interface switching circuit which is arranged on a first circuit board and a second circuit board. The first circuit board is provided with a Type-C interface, a protocol configuration chip, a HUB module, a video interface module, a USB interface module, and a network interface module. The second circuit board is provided with a power module. The Type-C interface is connected to the HUB module, the video interface module, and the protocol configuration chip respectively. The HUB module is connected to the USB interface module, the protocol configuration chip and the network interface module respectively, and the video interface module is connected to the protocol configuration chip. The first circuit board is electrically connected to the second circuit board, so that the power module is electrically connected to the Type-C interface, the protocol configuration chip, the HUB module and the network interface module.

Abstract: An electronic control unit (ECU) is disposed in a vehicle, and includes an input section and a controller. The input section inputs vehicle data from vehicle sensors and actuator to the controller. The controller includes a priority setter and a transmission data generator. The transmission data generator transmits transmission object data, which is data for transmission to an external device and generated from the vehicle data. The priority setter sets priority of the transmission object data based on priority setting data, which is data included in the vehicle data. The transmission data generator performs an adjustment process for adjusting an amount of transmission data based on the priority. The ECU provides an efficient transmission of data by limiting and/or preventing an increase in the amount of transmission data.