Abstract: A monolithic semiconductor device includes a field effect transistor and a bipolar junction transistor with a pillar emitter structure. The pillar structure raises the BJT emitter above the surface of a trenched base. Ions implanted into the base trench diffuses into an extrinsic base contact region. The pillar elevation structure increases travel distance between the trench and the emitter and protects against encroachment without increasing the total emitter area allocated to the BJT device. A spacer oxide adjacent to the pillar separates the pillar from the trench-region implanted with ions.

Abstract: An inverter device includes plural modules, each module being formed by a series circuit having a parallel circuit of a switching device and a first diode, and a parallel circuit of a second switching device and a second diode, allowing a reduced size, high reliability, high frequency switching and low noise. Each of the semiconductor modules includes a plurality of switching device chips and at least one diode chip formed on a metal substrate. Electrode plates are provided in locations of the module adjacent to the switching device chips and the diode chips to facilitate connection of the electrodes of the respective chips to one another and to the outside of the module.

Abstract: A semiconductor plastic package, more particularly a preferred package structure and method for making a BGA package. A resin sealed BGA package where a supporting frame which fixedly supports semiconductor parts; i.e., an IC chip, a circuit board, or a circuit film, is sealed with resin, using a mold which is composed of an upper mold half and a lower mold half with the lower mold half having a plurality of projections, one at a position corresponding to each of the external terminals. The mold has a divisional structure which has an air vent between the divisional elements thereof.

Abstract: A stackable heat sink assembly is formed by press-fit assembly of two or more identical fin layers. Each fin layer is formed using powdered metallurgy and has a button-like projection extending from its bottom surface and a recess opening in its top surface. The button-like projection and recess opening are sized and shaped such that an interference fit is formed when the button-like projection of one fin layer is pressed into the recess of another fin layer. The use of an adaptor to increase or decrease the effective size of the button-like projection of the bottommost fin layer is described. Relieving gases that may be entrapped in the recess during assembly is described. Circular, elliptical and polygonal shapes (outlines) for the fin layers are described.

Abstract: An integrated circuit assembly is formed with an integral power supply decoupling capacitor for monolithic circuitry in a semiconductor substrate by using the substrate itself as one plate of the capacitor. A dielectric is formed on the "back" side, or surface, of the substrate (i.e., the surface opposite the surface in which component structures are formed) such as by growing a native oxide thereon. Using a conductive epoxy, the back side of the substrate (actually, the dielectric layer thereon) is then attached to a conductive foundation member, which forms the other plate of the capacitor when a potential is applied across the substrate and the foundation member. The conductive foundation member also may be connected to a heat sink structure integral with the package. The heat sink may extend through a window in the package, providing a path and surface via which heat may be transferred to an external heat sink if a larger heat sink mass is needed.

Abstract: An RF power transistor package is configured for mounting to a heat sink in a multi-layer pc board, and includes a direct top side electrical ground path from a transistor chip located atop a ceramic substrate to a mounting flange, without passing through the ceramic substrate by way of metal plating an outer surface of the ceramic substrate to electrically connect a top mounted metal lead to the flange. A direct ground path from the transistor chip to the mounting flange is also provided by way of plated via holes through the ceramic substrate. The top side ground path is also configured to connect with the middle ground reference layer of the multi-layer pc board when the mounting flange is secured to the heat sink, so that a unified ground potential is seen by the transistor at both the middle layer and heat sink.

Abstract: In a packaging arrangement suitable for semiconductor devices, a semiconductor chip is mounted on a surface of an aluminum base with a bonding layer interposed therebetween. The aluminum base has a capability to favorably dissipate heat from the semiconductor chip. The bonding layer consists of a resilient and heat conductive material such as silicone resin mixed with silver powder so that thermal strain of the metal base is accommodated by the resiliency of the bonding layer, and is prevented from adversely affecting the electronic component chip even though the aluminum base demonstrates a substantially more significant thermal expansion than the semiconductor chip. It is therefore possible to achieve a high reliability in the packaging of semiconductor devices at a minimum cost.

Abstract: A semiconductor die is attached to a transistor package by a plurality of resilient clamping members, which are bonded at one end to a top surface of the semiconductor die and at another end to a stable surface, such as an emitter, collector, or base lead frame, of the transistor package. The shape and composition of the clamping members provides a resilient force that causes a bottom surface of the die to make and maintain substantially uniform and constant contact with the die attach area of the transistor package, e.g., a mounting flange or non-conductive substrate. The clamping members are preferably conductive and can conduct current from respective transistor cell locations on the die to the respective lead frames to which the clamping members are bonded.

Abstract: A semiconductor device and a method of manufacturing the same are provided which comprises a metal interconnection consisting of a titanium-aluminum film with (111) orientation formed on a semiconductor substrate via an insulating film, and an aluminum film or an aluminum alloy film with (111) orientation formed on the titanium-aluminum film by virtue of epitaxial growth. With such structure, electromigration endurance of an aluminum interconnection is improved and a wiring structure of a semiconductor is achieved with high reliability.

Abstract: An image sensor assembly is mounted in an optical system having a plurality of reference locators. The image sensor assembly includes an image sensing device having photolithographically generated elements, such as image sensing sites, and a carrier package for enclosing the image sensing device. The carrier package has externally accessible reference features that are optically aligned with respect to the photolithographically generated elements on the image sensing device. Moreover, the externally accessible reference features are used to exactly constrain the image sensor assembly relative to the reference locators. Referencing the image sensing device to the same features that are used for exact constraint removes the effect of material variations that may cause dimensional changes and eliminates the need to activate the sensor for alignment of the sensor assembly in the optical system.

Abstract: In a semiconductor substrate of a semiconductor device, a plural impurity layers of the same conductivity type as the substrate are formed. An impurity region of an opposite conductivity type penetrates at least one of the impurity layers to a certain depth from the main surface of the semiconductor substrate. The bottom surface of the impurity region terminates between the impurity layers where the impurity concentration is lower. A contact conductor is led out from the impurity region.

Abstract: A method and device for interconnecting stacked semiconducting plates, in which each of the plates has an integrated circuit. The semiconducting plates (P) are stacked and made solid with each other. In one embodiment, their connecting contacts are connected by a wire (F) to any one of the faces of the stack except one (B), which is to be in contact with a printed circuit. Connections of the plates together and with the printed circuit is made on the faces (F.sub.V, F.sub.S, F.sub.L) of the stack.

Abstract: A device or die is presented which uses laser deposited leads, with a filler to bridge the gap between the die and the lead frame. The filler may be oxide, poly amide, a combination of oxide layers and poly amide layers, plastic or a plastic which has plastic coated beads of metal. The die and lead frame are placed on a heat spreader. Leads are formed over the filler material from bond pads on the lead frame to bond pads on the die. Various protective materials are placed over the die to protect it from the package. Over the protective material is another heat spreader or other device that is required to make the die function better. Typical devices are batteries, capacitors, or other die. Finally, the structure is encapsulated in a package of non-conductive material. This structure is more stable than presently available structures because the active element, the die, is not in direct contact with the plastic package.

Abstract: A heat sink for semiconductor components has a fin base and a plurality of spaced fins that all have the same height. A side of the base facing the fins is configured convexly with respect to the side of the fin base facing the semiconductor component, so that when the heat sink is used as intended, the roots of its fins are arranged on a surface of constant temperature. This yields a finned heat sink that attains a heat flux density hitherto achievable only with evaporative or fluid coolers.

Abstract: An integrated semiconductor circuit, such as an A/D converter, includes a first zone having capacitors disposed therein. The capacitors have capacitor plates being formed of a first conductive layer and a second conductive layer. A second zone has circuit elements disposed therein. A planarizing layer and a cover layer insulate the first and second conductive layers from one another in the second zone, except for a possible peripheral region. A dielectric is formed only of the cover layer between the capacitor plates in the first zone, except for a possible peripheral region.

Abstract: An adhesive composition including: a main component comprising a resin material, a solvent for dissolving said main component, and a filler added to said main component, wherein said filler has a particle size so as to make a concavo-convex depth of a surface of said adhesive composition equal to or less than 15 .mu.m after said adhesive composition is applied to an adherend and dried in order to evaporate said solvent before a thermocompression process. The present invention also discloses a semiconductor device using the adhesive composition, an adhering method using the adhesive composition and a method for producing a semiconductor device using the adhesive composition.

Abstract: A clip secures a heat sink having a slot with grooves on opposing sides thereof to a transistor. The frame has sides with a width therebetween which can be wedged into grooves on opposing sides of a slot in the heat sink. A portion of the frame is raised up between two parallel cuts in the frame. A transistor is wedged under the raised up portion. The clip has legs which are insertable into a printed circuit board for easy assembly of a heat sink, transistor, clip and printed circuit board.

Abstract: Disclosed is an optical package which is economical to manufacture. An optical component, such as a PIN photodiode, is bonded to a substrate such as silicon with no metallization on its side surfaces. The resulting assembly is solder bonded to the bottom surface of the package so that a side surface of the substrate is adjacent to the bottom surface with essentially no solder therebetween.

Abstract: An electronic circuit apparatus has first and second pad electrodes arranged on a substrate to be separated by a first interval, first and second chip electrodes to be separated by a second interval smaller than the first interval, a first solder for fixedly attaching the first chip electrode to the first pad electrode and a second solder for fixedly attaching the second chip electrode to the second pad electrode. Because the first interval is longer than the second interval, any constricted portion does not exist in each of the first and second solders. Therefore, because any stress is not concentrated on any portion of each of the first and second solders, the occurrence of a crack in each of the first and second solders can be prevented.

Abstract: A wire bonding method for joining a metal wire with a bonding pad disposed on a semiconductor element by using a load and supersonic wave vibration, comprising: during interval of time from contact of the metal wire with the bonding pad to application of the supersonic wave vibration, continuously applying a first bonding load and a second bonding load which is lower than the first bonding load; and after application of the supersonic wave vibration, continuously applying a third bonding load of a size of about 50% of the load of the second bonding load and a fourth bonding load which is lower than the first bonding load and higher than the third bonding load. The reliability of the fine wire bonding joint is improved remarkably, whereby a high quality semiconductor device cna be produced at a low cost.