Abstract: A ceramic substrate having on the surface thereof a plurality of pads to be attached to terminal members is provided. Each pad includes a metallic layer formed on the surface of the substrate and a connecting layer made of a nickel base alloy and formed on the metallic layer. A gold-nickel layer made of a gold base alloy containing nickel is formed on the connecting layer. The gold-nickel layer may be formed by first forming a gold layer on the connecting layer and then making nickel in the connecting layer to diffuse into the gold layer by heat treatment. A method of producing such a ceramic substrate is also provided.

Abstract: A multi-layer bottom lead package of the present invention has semiconductor chips having: (a) bonding pads; (b) an insulating circuit film including (i) an insulating base film with through holes, (ii) first metal lines formed on upper and lower faces of the base film, (iii) protruding, conductive inner pads which are respectively formed on the first metal lines, being respectively connected to said bonding pads of each semiconductor chip, (iv) protruding, conductive outer pads which are formed on the first metal line, and (v) second metal lines formed along wall surface of the through holes to connect to the inner pads of each semiconductor chip; (c) a lead frame including an inner lead and outer lead for electrically connecting the outer pads of the insulating circuit film to an external device; and (d) a package body of encapsulating a predetermined area containing the semiconductor chips, the insulating circuit film and the inner leads of the lead frame, including a plurality of dimples formed at electri

Abstract: A semiconductor package for preserving clearance between encapsulant and a printed circuit board is provided including a package substrate having an upper surface and a lower surface, wherein the upper surface is attached to a heat spreader and the lower surface is electrically coupled to a printed circuit board by a plurality of high temperature solder balls, the solder balls being formed from a metal such as lead, tin or copper; a semiconductor die, the non-active side of which is coupled to the heat spreader, and which is electrically coupled to the substrate by bond wires joining bond pads on the active side of the semiconductor die to electrical traces formed on the package substrate; an encapsulant covering the semiconductor die and the bond wires such that the encapsulant forms a protrusion from the lower surface of the package substrate; and a lid having a plurality of stand-off legs, each leg being formed at a corner of the lid, disposed over the encapsulant which establishes the height of the protru

Abstract: The power MOSFET includes a substrate of the power MOS type FET having a source electrode, a part of which corresponds to a source pad area formed directly thereon. The device also includes a bonding wire for connecting the source electrode to the outside. The bonding wire is melt-bonded on the source pad area by an ultra-sonic vibration having a frequency of about 50 to about 70 kHz.

Abstract: A structure and method for controlling the junction temperature of a semiconductor chip in an electronic system. A temperature sensing device and the chip whose junction temperature is to be monitored are located adjacent to one another on the same interconnect structure. A thermally conductive lid can also be attached to the interconnect structure, thereby enclosing the temperature sensing device and the chip within in a closed cavity. Dedicated pins extend from the temperature sensing device through the interconnect structure, for connection to a temperature control circuit. By locating the temperature sensing device on the same interconnect structure as the chip, and within a common enclosure, the temperature sensed by the temperature sensing device is an accurate representation of the actual junction temperature of the chip. By obtaining an improved reading of the actual junction temperature, the operation of the temperature control circuit can be optimized.

Abstract: An inductive structure for an integrated circuit. The inductor has a first turn that shields the other turns of the inductor from a proximate ground plane. Multiple turns are disposed one above another in respective metalization layers of the integrated circuit. The turns are partial loops and are electrically coupled end-to-end with vias. Predetermined ones of the turns have additional portions in different layers. An additional portion of a turn is an electrically conductive strip deposited above the turn in a higher metalization layer and electrically coupled to the turn, thereby increasing the surface area of the turn and decreasing resistance of the turn. A buried n-type loop disposed below the first turn and below the surface of the substrate shields the first turn from the capacitive effects of the substrate.

Abstract: A ceramic package and mounting structure which requires less surface area on a heat sink and improves heat transfer to the heat sink. Each ceramic package has a top side and a bottom side with the bottom side being flat and smooth. The bottom side can be a polished ceramic, or metal layer which is plated or brazed to the bottom side. The mounting structure includes a clamp and a spring in pressure engagement with the top side of the package for maintaining the package in pressure engagement with the heat sink.

Abstract: A ceramic package and mounting structure which requires less surface area on a heat sink and improves heat transfer to the heat sink. Each ceramic package has a top side and a bottom side with the bottom side being flat and smooth. The bottom side can be a polished ceramic, or a metal layer which is plated or brazed to the bottom side. The mounting structure includes a clamp in pressure engagement with the top side of the package and maintains the package pressure engagement with the heat sink.

Abstract: The present invention is characterized by providing leads not contributing to actual connection outside the corner leads to prevent the deformation of the corner leads and improve the yield of tape carriers. A device hole is made in a near-central place of an insulating resin film. Around the device hole, outer-lead holes are made. On the insulating resin film, a plurality of wiring patterns are provided and forced to project into the device hole. The plurality of wiring patterns are formed into a plurality of inner leads, of which the outermost ones are determined to be corner leads. On each corner of the device hole, an aligning mark is provided. Dummy leads are provided closer to the aligning marks. The dummy leads are made shorter than the inner leads and corner leads.

Abstract: A method of manufacturing a semiconductor device which includes a semiconductor chip and a plastic package of a thermosetting polymer encapsulating the semiconductor chip through a molding process. The thermosetting polymer of the plastic package fully or partially covers a bottom surface of the semiconductor chip. An ultraviolet cleaning process is performed for cleaning the bottom surface of the semiconductor chip prior to the molding process.

Abstract: A reusable metal frame for manufacturing of encapsulated semiconductor devices includes a metal sheet having a plurality of openings disposed in compliance with topology of semiconductor devices carried by a supporting structure. During the molding operation, the frame is superposed over the supporting structure with each semiconductor device to be encapsulated, positioned centrally within one of the openings. The encapsulating material (resin, plastic, or the like) is supplied to each semiconductor device and stays within each opening, held in place by continuous uninterrupted contour of each opening. After the encapsulating material has been cooled, the metal frame is readily removed, and may be used in other molding operations.

Abstract: An electronic component provided with a heat radiative ceramic plate that is protected from cracks. Such a heat radiative electronic component is composed of an electronic device, such as a semiconductor device with an integrated circuit built therein, having a heat radiative plate bonded on its upper surface. The heat radiative plate is formed by a ceramic plate coated with a resin layer. The ceramic plate is a 1 mm to 2 mm thick quadrangular plate prepared by sintering cordierite powder, which has a high emissivity of far-infrared rays. The resin layer entirely or partly covers the surface of the ceramic plate, thereby preventing the plate from breaking and/or chipping and scattering ceramic powder to the surrounding area.

Abstract: Arrangement for the protection of electrical and electronic components against electrostatic discharge, where a printed circuit board on which the components are mounted is physically connected to a metal plate via an insulating layer with the insulating layer having at least one conductor track of the printed circuit board opening over which at least one track is placed to form a first spark gap between the track and the metal plate and with the metal plate being connected to a fixed potential.

Abstract: A semiconductor device which includes a ceramic package main body, a semiconductor element and a closure for sealing the semiconductor element in the package. A capacitor is formed on an upper or lower surface of the closure. The capacitor has a dielectric film interposed between a pair of electrode films. The dielectric film includes a ceramic filler and an amorphous glass. The closure and the package main body are sealed. A terminal formed in the package main body and the electrode film of the capacitor are connected electrically. High-density packaging on a substrate can be achieved. High strength of the closure itself can be maintained. Thermal stress developed in the closure itself, or the conjugated portion between the closure and the package main body, can be suppressed. Reliability of a sealed structure in the semiconductor device for a long period of time can be increased.

Abstract: A semiconductor device has a semiconductor chip mounted on the mounting portion of a lead frame and sealed with resin. The chip is affixed to the lead frame by melting. A groove is formed in the lead frame in a cruciform, radial, lattice or similar pattern capable of reducing thermal stress during intermittent performance test and cycling test while insuring heat radiation.

Abstract: A single leadframe package having stacked integrated chips mounted therein provides multiple electrical functions. The leadframe package construction includes a leadframe die having a substantially smaller outer peripheral dimension than a first integrated circuit chip mounted face down thereon for supporting from below the first integrated chip without obstructing its bond pads. A second integrated circuit is supported from below in a backside to backside configuration by the first integrated circuit without obstructing the bond pads of the second integrated circuit. A plurality of substantially short conductive wires interconnect electrically the first and second integrated circuit chips with selective ones of a plurality of leadframe conductors. An encapsulating material molds the construction into the single leadframe package.

Abstract: Improved manufacturability, yield, and reliability are achieved during wirebonding of a semiconductor die of reduced size by employing two rows of staggered conductive connectors, or bond pads, for wirebonding the die to a semiconductor package. An outer row of conductive connectors is positioned closer to the edge of the die than an inner row of conductive connectors and includes a greater number of connectors than the inner row. The die can be wirebonded to a package substrate having either a single row of bondfingers or multiple rows of bondfingers. In one embodiment, bond wires attaching the inner row of conductive pad connectors to the package substrate have a greater loop height than bond wires attaching the outer row of conductive pad connectors to the package substrate.

Abstract: A semiconductor device including a plurality of grooves (21) formed on a top surface of a heat sink (51). A sealing resin (2) fills a portion between a lead frame (5) provided facing the top surface and the heat sink (51). The grooves (21) are formed on both sides of a center region (22) extending so as to divide the top surface in two. A power semiconductor element (11) is disposed above the center region (22) and a controlling semiconductor element (16) controlling the power semiconductor element (11) is disposed above the region where the grooves (21) are formed. The above construction suppresses thermal resistance interposed in a path through which heat loss in the power semiconductor element (11) is radiated to the heat sink (51) and improves heat radiating efficiency while maintaining close contact between the sealing resin (2) and the heat sink (51).

Abstract: A semiconductor component has at least one semiconductor chip mounted on a carrier part of its housing. The semiconductor chip is electrically connected to at least two electrode connectors which are provided with contacts. The component housing has an upper housing portion and at least one housing side part which surround the semiconductor chip at least partially. The carrier part on which the semiconductor chip is mounted forms the upper housing portion of the component housing and the at least two electrode connectors at least partially form the housing side parts of the component housing.

Abstract: A plurality of bumps formed of low melting metal are disposed on the surface of the peripheral portion of a semiconductor substrate. Those bumps which are included in the above bumps and formed on each corner portion of the semiconductor chip are connected to a power supply wiring and a ground wiring used as a power supply wiring. The other bumps disposed in position other than the corner portions are connected to a signal wiring.