Abstract: A semiconductor element cooling apparatus adapted to cool at least one semiconductor element mounted on a circuit substrate. The semiconductor element cooling apparatus includes a first mechanism for generating a coolant flow by flowing a coolant over a top surface of the semiconductor element, and a second mechanism for obliquely obstructing the coolant flowing over the semiconductor element from an upstream side towards a downstream side of the coolant flow.

Abstract: An electronic package which includes a flexible substrate, stiffener and chip. The chip is bonded to the substrate, which was secured to the stiffener. Strain relief means are utilized at various locations in the package to prevent problems (e.g., tape "wrinkling") associated with relatively large differences in coefficients of thermal expansion between the package's various elements.

Abstract: A semiconductor apparatus includes a semiconductor chip having an upper surface, a lower surface and at least one side surface; a first radiator plate for radiating heat including a plate portion having an upper surface, a lower surface and at least one side surface and a body portion having an upper surface, a lower surface and at least one side surface. The upper surface of the body portion has an area smaller than an area of the lower surface of the plate portion and is connected with the lower surface of the plate portion. The semiconductor apparatus also includes a second radiator plate for radiating heat including an upper surface, a lower surface and at least one side surface. The upper surface of the second radiator plate has an area larger than the lower surface of the body portion of the first radiator plate.

Abstract: Lead On Chip ("LOC") leadframe designs for thin, small-outline packages having improved configurations of leadframe members are provided. The LOC leadframes comprise a bus bar, having at least one distribution finger, and a plurality of lead fingers arranged in such a manner that jump-over is eliminated, thus increasing the reliability of the package.

Abstract: It is an object to facilitate assembly of an application device. A device (101) is provided with a heat sink (51) to radiate loss heat of an IGBT element (11) as a power semiconductor element to an external radiation fin. External terminals (5 and 6) connected to an external circuit substrate protrude in the direction in which the exposed surface of the heat sink (51) is directed. Accordingly, when assembling an application device by mounting the device (101) on the external circuit substrate together with other circuit elements, it is possible to mount the device (101) and other circuit elements together on the common main surface of the circuit substrate, i.e., on its main surface on the side opposite to the side where the radiation fin is attached. Accordingly, it is possible to collectively apply solder on the common main surface of the circuit substrate and collectively solder the device (101) and the other circuit elements.

Abstract: A laser-tunable semiconductor device assembly (LSDA) is provided for electrical connection between multiple semiconductor devices (101, 103) within a RF transistor (100). The LSDA (100) provides for flip-chip type electrical connection between semiconductor devices (101, 103) utilizing solder bumps (503) existing on the semiconductor devices (101, 103) or the LSDA (100). A metalization pattern exists on both sides of the LSDA (100), electrically connected through via holes (403) existing in the LSDA (100). Laser tuning metallic pads (405) are provided for performance matching of the transistor. The use of the LSDA (100) provides for accurate modeling of the electrical connection between semiconductor devices (101, 103), while allowing for "on-line" process control of electrical performance of the transistor and acceptable heat dissipation through the bottom of the semiconductor devices (101, 103).

Abstract: A method in which several high voltage chips may be packaged within a single, typically low voltage plastic package. The high voltage chips are packaged to remain electrically isolated from each other to avoid undesirable side effects such as arcing between the chips but able to share electronic data and communicate with each other electronically through their input and ouput nodes. Due to the unique packaging method, the typically low voltage plastic packaging can be made to withstand operating voltages up to 35 times greater than previously attained by such low voltage plastic packaging.

Abstract: In a semiconductor device comprising an IC chip (8) mounted on a circuit substrate (7) and sealed with a molding resin (11), corner resist films (6a, 6b, 6c, 6d) are formed at positions corresponding to a corner A of the IC chip (8) on the circuit substrate (7), and the corner A of the IC chip (8) is bonded to these corner resist films by using a die bond (9). A die pattern (3a) is exposed outside the corner resist films, and a power supply pattern (3b) is so formed to encompass their periphery. The power supply terminal, the die pattern (3a) and the power supply pattern (3b) are connected to the IC chip (8) of the corners of the IC chip is improved and peel is prevented. Furthermore, bonding of a large number of bonding wires for supplying power can be freely made.

Abstract: An integrated circuit package assembly with a first die disposed over a first substrate having traces defined therein to provide electrical access to the first die. A heatsink is disposed over the substrate and the first die. A second die and a leadframe is disposed over the heatsink. The leadframe provides electrical access to the second die.

Abstract: The present invention relates to a pad for connecting external connection terminals such as bonding wires to IC chip. The present invention provides a semiconductor device having upper and lower electrode layers and an interlayer insulation film therebetween, the interlayer insulation film including a through hole which is formed therethrough at a given location. An interlayer connection conductor is embedded in the through hole. For example, the ball-like portion of the bonding wire may be connected to the upper electrode layer such that the ball-like portion perfectly covers the embedded conductor. Such an arrangement will not create any step. Therefore, the bonding area can be easily ensured to facilitate a further formation of more layers. The embedded metal will not be adversely affected by moisture moved into along the bonding wire. The external connection terminal may be of any suitable form such as bump electrode and film carrier.

Abstract: A power module has a metallic base plate layer and a substrate layer that has a first metallic layer, a dielectric layer, and a second metallic layer. A solder layer thermally and electrically connects the second metallic layer to the base plate. A plurality of silicon dice are mounted to the first metallic layer of the substrate. The solder layer has a void development region which after a predetermined number of thermal cycles does not significantly increase. The silicon dice are oriented on the substrate layer so that the silicon dice are not aligned over the void development region corresponding to the useful life of the module. The metallic base plate may also be mounted to a heatsink through a thermal grease layer. The heatsink may comprise the outer covering of the power module.

Abstract: A flexible resin substrate with a device hole at the center thereof is formed wiring leads with copper foil on the back side face. A tape carrier having such construction forms substrate of a package. The wiring leads are formed to extend from the back side face of the flexible resin substrate into a device hole. The extended portions of the wiring leads are stepped within the device hole to form the inner leads. On the other hand, the wiring leads have lands provided greater width than other portions at the portions located on the back side face of the flexible resin substrate. A semiconductor chip is formed with bump elements of Au or so forth, on the surface side face and oriented directing the surface where the bump electrodes are formed downwardly and arranged within the device hole. The bump electrodes are connected to the inner leads of the tape carrier by batch bonding. On the other hand, the lands are arranged in a form of grid array. Solder balls are fixed on respective lands to form bumps.

Abstract: A heat sink comprising a bottom plate and a plurality of fin groups on the bottom plate is disclosed, the plurality of the groups being spaced from one another, and aligned in a matrix form or arranged in a staggered pattern, and each of the group comprising a plurality of plane parallel plates or pins that are integral with the bottom plate.

Abstract: Ends of inner leads are disposed in the vicinity of a peripheral end of a semiconductor chip and a portion of an insulating film tape is affixed to a main surface of the semiconductor chip by an adhesive while other portions of the insulating film tape are affixed to portions of the inner leads by an adhesive. Electrode pads provided in the main surface of the semiconductor chip are electrically connected to the ends of the corresponding inner leads by bonding wires, and the semiconductor chip, the inner leads, the electrode pads, the insulating film tape and the bonding wares are sealed by a resin molding. The thickness of the insulating film tape is smaller than a height from the main surface of the semiconductor chip to an apex of the bonding wire. Surfaces of the ends of the inner leads connected to the bonding wires are positioned lower than the main surface of the semiconductor chip and the inner leads are positioned between the main surface and an opposite surface of the semiconductor chip.

Abstract: A fabrication method and resultant monolithic electronic module having a separately formed thin-film layer attached to a side surface. The fabrication method includes providing an electronic module composed of stacked integrated circuit chips. A thin-film layer is separately formed on a temporary support which is used to attach the thin-film layer to the electronic module. The disclosed techniques may also be used for attaching an interposer, which may include active circuity, to an electronic module. Specific details of the fabrication method, resulting multichip packages, and various thin-film structures are set forth.

Abstract: This invention is a process for forming an effective titanium nitride barrier layer between the upper surface of a polysilicon plug formed in thick dielectric layer and a platinum lower capacitor plate in a dynamic random access memory which is being fabricated on a silicon wafer. The barrier layer process begins by etching the upper surface of the polysilicon plug using a selective polysilicon etch until it is recessed at least 1000 .ANG. below the upper surface of the thick dielectric layer. Using a collimated sputter source, a titanium layer having a thickness of 100-500 .ANG. is deposited over the surface of the in-process wafer, thus covering the upper surfaces of the polysilicon plugs. A layer of amorphous titanium carbonitride having a thickness of 100-300 .ANG. is then deposited via low-pressure chemical vapor deposition. This is followed by the deposition of a reactively sputtered titanium nitride layer having a thickness of 1000-2000 .ANG..

Abstract: A semiconductor device having a silicide layer with substantially even thickness, and a method for making a silicide layer having substantially even thickness in a semiconductor device are disclosed.A prefereably doped polycrystalline silicon layer is formed as a first conductive layer on an insulating underneath layer. After that, an undoped polycrystalline silicon is deposited on the first conductive layer as a buffer layer for preventing silicon diffusion. A second conductive layer is formed thereon. Subsequently, a refractory metal layer is formed on the second conductive layer, and a heating treatment is carried out to form a silicide layer on the first conductive layer from the materials of the buffer layer, second conductive layer and refractory metal layer.

Abstract: A semiconductor device of the present invention includes an insulating layer covering a plurality of semiconductor elements formed in a semiconductor layer, an opening portion formed in the insulating layer respective conductive porions of the plurality of semiconductor elements in the insulating layer, and a conductive pattern formed in the opening portion for connecting respective conductive portions of the plurality of semiconductor elements.

Abstract: After a pattern transfer of a first pattern image to a lower photo-sensitive layer of first material, a second pattern image is transferred to an upper photo-sensitive layer of second material higher in photo-sensitivity than the first material, and the first image and the second image are concurrently developed so as to form a composite etching mask through a simple process.

Abstract: This invention is discloses a packaged integrated circuit (IC) which includes an IC chip supported and securely attached to an adapter board. The package also includes a chip cap for covering and protecting the IC chip therein. The chip cap further forms a concave, step near a lower edge of the cap for wrapping around the edge of the adapter board for increasing the contact areas between the cap and the board and for securely attaching the cap to the board. The chip cap is composed of thermal conductive materials and the chip cap further includes a heat sink for dissipating heat generated from the IC chip. The adapter board further includes a plurality of connecting vias and a plurality of conductive metal balls forming a ball grid array (BGA) underneath the adapter board. The IC chip is in electrical and thermal contact with the BGA by filling the connection vias with conductive materials.