Abstract: A semiconductor device capable of preventing the occurrence of defect of electroconductivity, wherein a semiconductor chip 1 equipped with electrodes 11 is mounted on an auxiliary wiring plate 2 in the state of facing the surface of the electrode 11 side, leading conductors 23 are disposed in the inside of the auxiliary wiring plate 2, one end of each leading conductor 23 forms an internal electrode 21 projecting from the surface of the auxiliary wiring plate 2 at the side of mounting the semiconductor chip 1, the other end of the leading conductor 23 forms an external electrode 22 projecting from the surface of the auxiliary wiring plate opposite to the side of mounting the semiconductor chip 1, and each of the internal electrodes 21 is connected to each of the electrodes 11 of the semiconductor chip 1, at least a gap between the semiconductor chip 1 and the auxiliary wiring plate 2 is encapsulated with a heat-welding polyimide resin layer.

Abstract: A film carrier tape and laminated multi-chip semiconductor device incorporating the same and method thereof wherein a plurality of chip-semiconductor devices are laminated onto a substrate. Each chip semiconductor device includes a film carrier tape having leads, a semiconductor chip electrically connected to the leads, a heat sink mounted to a surface of the chip, and a connector for mounting the heat sink, the connector being electrically connected to the leads of the film carrier tape. The film carrier tape includes a carrier member having a metallic layer superposed thereon which is etched so as to form the leads and the heat sink.

Abstract: A stacked chip package comprising an upper part including an upper semiconductor chip having a plurality of electrode bonding pads disposed on a central region of an active surface of the semiconductor chip; an upper lead frame having leads extending over the active surface of the upper semiconductor chip and which are electrically interconnected to the electrode bonding pads of the semiconductor chip; a lower part including a lower semiconductor chip having a plurality of electrode bonding pads disposed on a central region of an active surface of the semiconductor chip; a lower lead frame having inner leads extending over the active surface of the lower semiconductor chip which are electrically interconnected to the electrode bonding pads of the lower semiconductor chip, and outer leads for electrical interconnecting the stacked chip package to an external circuit device.

Abstract: An apparatus for integrating wafer scale semiconductor integrated circuits and interfacing them with other systems. A wafer, partial wafer, die or plurality of same are mated to a printed circuit board (PCB) which electrically contacts the pads on each die using small conductive pillars. The PCB in turn is connected easily to other electronic systems. The entire apparatus is incorporated into other systems which utilize the dice in the apparatus. The apparatus may be fitted with heating elements and cooling channels to generate the necessary dice temperatures for burn-in, testing, and operation. The apparatus is easily adaptable to include more dice in a stacked configuration.

Abstract: A leadframe that exhibits improved thermal dissipation and that can be incorporated in standard integrated circuit (IC) package designs is provided by extending the inner lead portions along a major surface of an IC, and attaching a heat sink on a side of the inner lead portions opposite the IC. The inner lead portions conduct heat from the IC to the heat sink, where it is dissipated into the moulding compound and radiated into the air. In the preferred embodiment, the leads have outer portions that are arranged on only two opposing sides of the IC package and comprise four sets of leads that initially intersect the IC along four lateral sides. This allows for a larger number of leads to contribute to heat dissipation. Added thermal dissipation is achieved by making the inner portion of a ground lead wider than the inner portion of any other lead.

Abstract: The present invention is provided with a transfer-mold package wherein the surface of a heat sink on which a semiconductor chip dissipating a large amount of heat is formed (the surface does not contact the chip) is exposed from the sealing resin. In this package, a concave portion 16a is formed in the surface of the heat sink to a depth of about 0.1 mm within a range of about 1 mm from the periphery of the heat sink. The concave portion prevents the sealing resin from extending toward the surface of the heat sink at the time of transfer mold, with the result that a resin burr can be prevented from occurring on the periphery of the surface of the heat sink exposed from the sealing resin, and the flatness of the surface of the heat sink can be prevented from being degraded by the resin burr.

Abstract: In a package including a substrate, a conductive layer formed within the substrate, an internal lead element connected via a first throughhole to the conductive layer, and an external lead element connected via a second throughhole to the conductive layer, notches are formed in the conductive layer in close proximity to the first and second throughholes.

Abstract: A heat sink is formed on a bonded semiconductor on insulator (SOI) wafer. A trench is formed which extends from a top of the bonded SOI wafer through an isolation region of the bonded SOI wafer to a base of the bonded SOI wafer. The base of the bonded SOI wafer is located below the isolation region of the bonded SOI wafer. A conductive pillar is formed in the trench. The conductive pillar extends from the top of the bonded SOI wafer through the isolation region of the bonded SOI wafer and is physically in contact with but electrically insulated from the base of the bonded SOI wafer. In the preferred embodiment, the conductive pillar is formed of doped polysilicon. The doped polysilicon is of a conductivity type which is different than the conductivity type of the base. Out-diffusion from the doped polysilicon forms a region within the base which electrically insulates the conductive pillar from the base.

Abstract: A lead frame includes first slits in a lead frame edge in a direction parallel to a longitudinal direction of the lead frame edge at spaced intervals and a plurality of slits in the lead frame edge in a direction parallel to the first slits at spaced intervals so that the second slits are separated from the first slits wherein each end of each of the second slits is located near the center of a corresponding first slit.

Abstract: A method for manufacturing a cap for use in a semiconductor package is disclosed. The semiconductor package includes a semiconductor chip and a substrate. The chip is mounted with the substrate at a chip locus. The method preferably comprises the steps of placing a slug in a die, and exercising the die to cold flow the slug to a predetermined cap configuration. The cap configuration includes a plurality of walls depending from a polygonal generally planar base and cooperating with the base to establish a well bounded by the walls and the base. The walls terminate in a plane, and the well clears the chip when the cap is mounted on the substrate at the chip locus. The invention further includes a cap for use in a semiconductor package. The cap comprises a structure cold flowed from a slug in a die to a predetermined cap configuration.

Abstract: A MOS type transistor with a gate is formed on the surface of a semiconductor substrate, and thereafter an interlayer insulating film and a first level wiring layer on the insulating film are formed. The wiring layer is patterned to cover the gate electrode. A second level interlayer insulating film is formed covering the wiring layer 16, and a second level wiring layer is formed on the second level interlayer insulating film. The second level interlayer insulating film is a laminate of a silicon oxide film formed by plasma CVD using tetraethoxysilane, a spin-on-glass (SOG) film, and another similar silicon oxide film, sequentially formed in this order. An auxiliary electrode layer (blocking layer) of the first level wiring layer covering the gate electrode prevents moisture contents from being diffused from the second level interlayer insulating film toward the gate electrode.

Abstract: A fabrication method and resultant monolithic electronic module having a separately formed thin-film layer attached to a side surface. The fabrication method includes providing an electronic module composed of stacked integrated circuit chips. A thin-film layer is separately formed on a temporary support which is used to attach the thin-film layer to the electronic module. The disclosed techniques may also be used for attaching an interposer, which may include active circuity, to an electronic module. Specific details of the fabrication method, resulting multichip packages, and various thin-film structures are set forth.

Abstract: A method of packaging an integrated circuit. An integrated circuit is connected to a substrate. A reservoir body is applied to the substrate, and the reservoir body and substrate define at least one reservoir and at least one flow gate. The reservoir body, substrate, and integrated circuit define a flow ring which extends at least partially around the circumference of the integrated circuit. A compound is dispensed into the reservoirs, and is flowed through the flow gates and into the flow ring, underfilling the integrated circuit.

Abstract: Electronic systems utilizing a plurality of integrated circuit packages having a stackable heat sink assembly is formed by press-fit assembly of two or more identical fin layers. Each fin layer is formed using powdered metallurgy and has a button-like projection extending from its bottom surface and a recess opening in its top surface. The button-like projection and recess opening are sized and shaped such that an interference fit is formed when the buttonlike projection of one fin layer is pressed into the recess of another fin layer. The use of an adaptor to increase or decrease the effective size of the button-like projection of the bottom-most fin layer is described. Relieving gases that may be entrapped in the recess during assembly is described. Circular, elliptical and polygonal shapes (outlines) for the fin layers are described.

Abstract: An overmolded plastic integrated circuit package which contains an integrated circuit that is mounted to a first surface of a printed circuit board. The integrated circuit is electrically coupled to a plurality of external contacts located on an opposite second surface of the printed circuit board. The integrated circuit is encapsulated and protected by a molded plastic compound. The printed circuit board has slots that receive a portion of the molded plastic material. The plastic filled slots anchor the outer encapsulant to the printed circuit board and prevent delamination between the interface of the circuit board and the adjacent encapsulant material.

Abstract: The first semiconductor package comprises a board equipped wiped with a wiring circuit including a connection on a main surface, a semiconductor chip mounted face down having input/output terminal corresponding to the connection of the board, flat external connector terminals leading to and are exposed on the other main surface of the board, and filled via hole connection to be electrically connected to the wiring circuit through a filled via hole installed right above each external connector terminal. Further, the second semiconductor package utilizes the above-described construction but the flat external connector terminals are led to and exposed on the other main surface of the board in a constant-pitch lattice-array.

Abstract: Disclosed is an integrated circuit configuration including a carrier having recesses for supporting individual semiconductor die units. The semiconductor die units and the carrier recesses have lithographically defined dimensions so as to enable precise alignment and a high level of integration.

Abstract: Techniques for providing semiconductor packages capable of forming connections to "high I/O" semiconductor dies is described, wherein there are at least two distinct pluralities of conductive lines. Leadframe-type packages and substrate-based package embodiments are described.

Abstract: A semiconductor device is disclosed which employs transfer molding to simplify a resin sealing step, reduces fabrication costs without using expensive elements, and has an improved efficiency of dissipation of heat generated by a power device and an improved product rating. The power device (101) and a control device (102) are placed in predetermined positions on horizontally positioned lead frames (103a, 103b), respectively. An insulating layer (105) of epoxy resin or the like is formed on a major surface of a heat sink (104), and a circuit pattern layer (106) formed on a major surface of the insulating layer (105) is shaped to conform to a predetermined circuit pattern. The lead frames (103a, 103b) are disposed on the circuit pattern layer (106).

Abstract: In a semiconductor device which has a base film sheet to support a semiconductor chip in a center region of the base film sheet, a plurality of via holes are formed within a peripheral region of the base film sheet. The via holes may be used to mount a metal plate on the base film sheet or to support another semiconductor chip, by forming ball bumps on or in the via holes. A circuit board may be attached to the base film sheet by the use of the bumps or pins extended through the via holes.