Abstract: A semiconductor device has a connection electrode and protective film formed of organic material and covering the connection electrode. An opening is formed in the protective film to expose the connection electrode. A natural oxide layer is etched by argon-based dry etching. The surface layer of the protective film is altered to reduce the insulativity in the dry etching process. After a projection electrode is formed on the connection electrode later, the altered surface layer of the protective film is removed by oxygen-based dry etching. As no altered surface layer remain on the protective film, an adverse affect such as inadequate insulation does not occur.

Abstract: A semiconductor ceramic multilayer package comprising an aluminum nitride substrate having a semiconductor element mounted on one surface thereof and a wiring pattern electrically connected to the semiconductor element, connecting terminals connected to the wiring pattern and disposed on the other surface of the aluminum nitride substrate, and a sealing member connected to the aluminum nitride substrate with a metallic bonding layer or a glass layer having a thickness of not more than 100 .mu.m in such a manner as to seal the semiconductor element possesses a notably improved heat-radiating property and accomplishes the object of increasing the number of pins and reducing the size of package.

Abstract: A vertical IGFET configuration includes a stripe arrangement having a non-linear shape. In one example, a stripe arrangement (30) has contact cut-out portions (41) and elongated portions (42). The elongated portions (42) have a width (44) that less than the width (43) of the contact cut-out portions (41). The stripe arrangement (30) increases channel density compared to typical individual cell configurations (10) and straight stripe configurations (20) thereby lowering on-resistance.

Abstract: An integrated circuit chip (100) includes an integrated circuit die (105) having first and second opposing surfaces (110, 115). A first integrated circuit (205) is formed on the first surface (110), and has a first plurality of terminals (200) coupled thereto for connection to first circuitry external to the integrated circuit chip (100), wherein the first plurality of terminals (200) is formed on the first surface (110). A second integrated circuit (300) is formed on the second surface (115), is electrically isolated from the first integrated circuit (205), and has a second plurality of terminals (305) coupled thereto for connection to second circuitry external to the integrated circuit chip (100). The second plurality of terminals (305) is formed on the first surface (110) and is coupled to the second integrated circuit (300) via plated holes formed through the integrated circuit die (105).

Abstract: Method of cooling electronic systems and semiconductor devices as well as an electronic system and a semiconductor device with heat dissipating elements. The method includes the steps of providing an electronic system or a semiconductor device with a heat sink including at least a first element having a generally flat shape with a shoulder projecting from one generally flat surface, and configured to thermally engage similar elements. In one embodiment, a first and a second heat sink element are provided, with one of the first and second elements having a protrusion and the other of the first and second elements defining a depression configured to receive and retain said protrusion. Alternatively, the first and second elements may be bonded together with a thermally conductive adhesive.

Abstract: The present invention is a sidewall connector providing a conductive path linking at least two conductive regions. The sidewall connector has a top portion comprising surface. A conductive member contacts the top portion, connecting the rail to a conductive region or to an external conductor. An etch stop layer located on a conductive region can be used to protect the conductive region during the directional etch to form the sidewall connector. A conductive bridge is then used to link exposed portions of the conductive region and the conductive sidewall rail, the conductive bridge extending across the thickness of the etch stop layer. A "T" connector is formed by the process, starting with a pair of intersecting sidewalls wherein the two sidewalls have top edges at different heights where they intersect. The connector is used to form a strap for a DRAM cell.

Abstract: A contact pattern for an integrated circuit package. The package has a plurality of contacts that are soldered to corresponding pads of a printed circuit board. The contacts are arranged into a plurality of cell units. Each cell unit has a row of center contacts diagonally located between two rows of outer contacts. The diagonally located pins increase the density of the contact pattern. Each unit cell is separated by a space that allows routing traces to be routed therethrough. Routing traces may also be routed through the unit cells to increase the routing density of the package. The package provides a contact pattern that optimizes both the pin density and the routing traces.

Abstract: A method and structure for attaching a lead frame to a heat sink are provided. In one embodiment, a layer of thermally conductive, electrically insulating epoxy is formed on a heat sink and the epoxy layer is fully cured. A thermoplastic adhesive layer is formed on the epoxy layer, and the heat sink is clamped to the lead frame such that the thermoplastic layer contacts the lead frame. The thermoplastic layer is heated to its melting point and then cooled, thereby joining the heat sink and the lead frame. In a variation, a partially cured B-stage epoxy layer is used to replace the thermoplastic layer. The B-stage epoxy layer is fully cured to connect the lead frame to the heat sink.

Abstract: Normal and reverse IC patterns are each a mirror image of the other. The normal and reverse IC patterns are simultaneously formed on a semiconductor wafer and are simultaneously tested. The wafer with these IC patterns is cut into chips, which are packaged. The normal and reverse IC packages show identical parasitic impedance and uniform performance.

Abstract: An electrical connection is provided between a 3-wire transmission line buried in a dielectric substrate and corresponding first, second and third conductive pads formed on a substrate surface. The 3-wire line includes first, second and third wires having a wire cross-sectional dimension. A tapered section connects each wire of the 3-wire line to a corresponding pad. Each tapered section increases in cross-sectional dimension from a first end connected to an end of the wire and a second end connected to a pad. The tapered sections provide a smooth transition of electromagnetic fields between the 3-wire line and the pads.

Abstract: A method for transfer molding a standard electronic package and an apparatus resulting from such method. A seal is formed between a portion of the mold platens of the mold and a portion of a printed circuit board adjacent to electrical contacts along at least one side of the printed circuit board. After the apparatus is removed from the mold, a protective cap is placed over the electrical contacts.

Abstract: A device and method for increasing integrated circuit density comprising a pair of superimposed dies with a plurality of leads extending between the dies. The device is produced by providing a lower die which has a plurality of bond pads on a face side of the lower die. A layer of dielectric or insulative shielding is applied over the lower die face side. Leads are applied to an upper surface of the shielding layer. A plurality of lower die bond wires is attached between the lower die bond pads and an upper surface of their respective leads. A second layer of dielectric or insulative shielding is applied over the leads and the portion of the lower die bond wires extending over the lead upper surfaces. A back side of the upper die is adhered to an upper surface of the second shielding layer. A plurality of upper die bond wires are attached between a plurality of bond pads on a face side of the upper die and the upper surface of their respective leads.

Abstract: An integrated circuit (IC) device package that includes permanent identification regarding the device characteristics, wherein the permanent identification are at or below the surface of the package and may indicate the operating frequency of an IC die within the package, as well as voltage requirements, etc.

Abstract: A lead frame for use in a resin-sealed type semiconductor device, comprising an outer frame, a plurality of leads supported by the outer frame, arranged side by side and each composed of an inner lead and an outer lead, a die pad arranged inside the outer frame and located so that the tips of the inner leads are close to the die pad and oppose the die pad, and a resin flow-control body. The resin flow-control body has been formed by extending a portion of the outer frame toward the die pad through a space formed in the outer frame. The body is designed to be placed in a cavity of a mold having a gate communicating with the cavity, with the space located between the gate and the cavity, in order to form a resin sealing body.

Abstract: An LOC type semiconductor package and a fabricating method thereof comprises first and second through holes formed at inner leads and bus bars of the LOC-type lead frame, and third through holes formed at the tape which is bonded with the lower side of the inner leads and the bus bars, by pins at a tape cutter. Thus, air existing at both tape during the bonding process effectively flows out so as to prevent the trapping of air bubbles. Accordingly, during the wire bonding process, wire shorting and damage to the package body can be prevented. Since EMC is deposited into the first and the second through holes and supports the inner leads and the bus bars during the molding of the semiconductor package, the reliability of the semiconductor package can be improved.

Abstract: A chip-sized semiconductor package having a semiconductor chip formed with bonding pads; a circuit board provided with contact pads for electrically connecting the circuit board to external terminals, and circuit patterns for electrically connecting the circuit board to the chip; a tape bonding the circuit board to the chip; and wires electrically connecting the circuit board to the bonding pads on the chip; the package being encapsulated by a molding compound so that a part of a surface of the circuit board where the contact pads are formed is exposed.

Abstract: An apparatus for integrating wafer scale semiconductor integrated circuits and interfacing them with other systems. A wafer, partial wafer, die or plurality of same are mated to a printed circuit board (PCB) which electrically contacts the pads on each die using small conductive pillars. The PCB in turn is connected easily to other electronic systems. The entire apparatus is incorporated into other systems which utilize the dice in the apparatus. The apparatus may be fitted with heating elements and cooling channels to generate the necessary dice temperatures for burn-in, testing, and operation. The apparatus is easily adaptable to include more dice in a stacked configuration.

Abstract: The present invention relates to a substrate for a semiconductor device having a diamond base material and a multisublayer wiring layer on the diamond base material, wherein the diamond base material is a diamond layer prepared by vapor phase deposition. The multisublayer wiring layer has at least one insulating sublayer having a relative dielectric constant of not larger than 5 or at least 12 and at least one metal wiring sublayer. The present invention is particularly useful as a substrate for a high performance, high-speed operation semiconductor device.

Abstract: A chip sized semiconductor device includes a semiconductor chip having upper and lower surfaces. The chip has electrodes formed on the upper surface thereof. An electrically insulating passivation film is formed on the upper surface of the semiconductor chip, except for areas where the electrodes exist. An anisotropic conductive sheet has an upper surface providing with a circuit pattern formed thereon and a second surface being adhered to the passivation film. The circuit pattern has inner and outer connecting portions. The electrically insulating film covers the upper surface of the anisotropic conductive sheet so that the outer connecting portions of the circuit pattern are exposed to be connected to external connecting terminals. The anisotropic conductive sheet is partially pressed at positions correspond to the electrodes, so that the inner portions of the circuit pattern are electrically connected to said electrodes of the semiconductor chip.

Abstract: A heat sink for mounting a semiconductor chip in a plastic casing. The upper surface of the heat sink is in thermal contact with the semiconductor chip, the lower surface is coplanar with a main surface of the casing. The heat sink is formed from a substantially square sheet of metal having each of its corners folded as a tongue to provide a substantially square base, each of the folded tongues forming the lower surface of the base.