Patents Examined by David Yi
  • Patent number: 11809718
    Abstract: A storage module includes a set of memories. Each of the memories in the set of memories may be divided into a set of portions. A controller is configured to transfer data between the set of memories and a host connected through an interface. A set of channels connects the set of memories to the controller. The controller is also configured to select: a memory from the set of memories, a portion from the set of portions for the selected memory, and/or a channel from the set of channels, e.g., connected to the selected memory, based upon an identification (ID) associated with the data. The ID may be separate from the data and a write address of the data, and the selected memory, the selected portion, and the selected channel may be used to store the data.
    Type: Grant
    Filed: May 21, 2021
    Date of Patent: November 7, 2023
    Assignee: Memory Technologies LLC
    Inventor: Kimmo Juhani Mylly
  • Patent number: 11809733
    Abstract: A method for storing data in a system that includes a plurality of storage devices, the method that includes obtaining object usage data from the plurality of storage devices, determining, using the object usage data, object clusters, where at least one object cluster of the object clusters includes at least two objects that are associated based on access patterns, migrate a first object, of the two objects, from a first storage device of the plurality of storage devices to a second storage device of the plurality of storage devices.
    Type: Grant
    Filed: December 9, 2022
    Date of Patent: November 7, 2023
    Assignee: DELL PRODUCTS L.P.
    Inventors: Kirill Aleksandrovich Bezugly, Nickolay Alexandrovich Dalmatov
  • Patent number: 11803330
    Abstract: The invention introduces a method for handling sudden power off recovery, performed by a processing unit of an electronic apparatus, to include: driving a flash interface to program data sent by a host into pseudo single-level cell (pSLC) blocks of multiple logical unit numbers (LUNs) in a single-level cell (SLC) mode with multiple channels after detecting that the electronic apparatus has suffered a sudden power off (SPO), and driving the flash interface to erase memory cells of all the pSLC blocks when data of all pSLC blocks has been read by the host. The pSLC blocks are reserved from being written to in regular operations until the SPO is detected.
    Type: Grant
    Filed: October 27, 2021
    Date of Patent: October 31, 2023
    Assignee: SILICON MOTION, INC.
    Inventors: Jieh-Hsin Chien, Yi-Hua Pao
  • Patent number: 11797218
    Abstract: A method for detecting a slow node includes: obtaining a generated record for a first storage node, the generated record including a storage node generation time, and a number of times and consuming time for transmitting data to second storage nodes other than the first storage node; obtaining a valid record from the generated record, the valid record being generated within a preset time period, and the preset time period being within a time period between the storage node generation time and a current time; determining an average consuming time for the first storage node transmitting the data to each of the second storage nodes, based on the number of times and the consuming time in the valid record; and detecting the slow node in the second storage nodes based on the average consuming time.
    Type: Grant
    Filed: April 23, 2020
    Date of Patent: October 24, 2023
    Assignee: Beijing Xiaomi Mobile Software Co., Ltd.
    Inventors: Haibin Huang, Lisheng Sun, Chen Zhang
  • Patent number: 11797210
    Abstract: A memory system includes a host device including a host controller, and a memory device including a device controller and a non-volatile storage including a purge region and a memory region. The device controller communicates purge information associated with the purge region and including size information of the purge region. The host controller communicates a request for generating a first partition for a first logical unit in the memory region, and communicates a request for generating a second partition for a second logical unit in the purge region in response to the size information of the purge region.
    Type: Grant
    Filed: July 7, 2021
    Date of Patent: October 24, 2023
    Inventors: Dae Jin Jung, Dong-Min Kim, Jeong-Woo Park, Kyoung Back Lee
  • Patent number: 11797200
    Abstract: A provided a storage device configured to support a number of namespaces. The storage device includes a memory and a controller coupled to the memory. The controller includes a host interface layer and a flash translation layer configured to report to the host interface layer a first over-provisioning chunk from an over-provisioning pool and a first chunk separate from the over-provisioning pool. The controller is configured to receive a command at the host interface layer to utilize a portion of the memory for a first namespace from among the number of namespaces and the first namespace includes an unaligned chunk. The controller is configured to utilize the first over-provisioning chunk as the unaligned chunk of the first namespace. A number of over-provisioning chunks to be utilized as unaligned chunks is less than the number of namespaces.
    Type: Grant
    Filed: February 25, 2022
    Date of Patent: October 24, 2023
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Xiang Lian, Chao Yang
  • Patent number: 11797211
    Abstract: A method for storage cluster expansion is provided. The method includes distributing user data throughout a storage cluster as directed by each of a plurality of authorities in the storage cluster. Each of the plurality of authorities has a plurality of wards, and each of the plurality of wards has ownership of a range of the user data. The method includes splitting one of the plurality of authorities, as a parent authority, into at least two child authorities and assigning a first subset of the plurality of wards of the parent authority to one of the at least two child authorities, and a second subset of the plurality of wards of the parent authority to another one of the at least two child authorities.
    Type: Grant
    Filed: July 29, 2022
    Date of Patent: October 24, 2023
    Assignee: PURE STORAGE, INC.
    Inventors: Robert Lee, John Martin Hayes, Faissal Sleiman
  • Patent number: 11797393
    Abstract: A system includes one or more source memory devices of a source computing environment that store a database comprising data files grouped in a plurality of file groups, wherein each of a plurality of data tables of the source computing environment includes data from one or more of the data files grouped in to one or more of the file groups, one or more target memory devices of a target computing environment and at least one processor configured to receive a command to copy data files from the source memory devices to the target memory devices, detect that the target memory devices have insufficient memory, calculate a value coefficient for each data table, assign a priority index to each data table based on the value coefficient, re-arrange the file groups based on priority indices of the data tables, and copy the re-arranged file groups to the target memory devices.
    Type: Grant
    Filed: March 23, 2022
    Date of Patent: October 24, 2023
    Assignee: Bank of America Corporation
    Inventors: Praveen Kumar Trivedi, Venugopala Rao Randhi, Anshuman Mohanty, Ritesh Kumar Dash
  • Patent number: 11789827
    Abstract: A cloud manager restores a backup of a distributed environment by comparing a stack of a current distributed environment to a backup stack of the backup of the distributed environment. The cloud manager identifies a difference between a first number of nodes in the first set of nodes specified in the first stack and a second number of nodes in the second set of nodes specified in the second stack. The cloud manager restores the backup of the distributed environment by modifying a number of nodes in the current distributed environment based on the identified difference between the first number of nodes and the number of nodes in the second stack.
    Type: Grant
    Filed: August 18, 2022
    Date of Patent: October 17, 2023
    Assignee: Oracle International Corporation
    Inventors: Biju Narayanan, Harish Subramanian, Jibu Thomas Thomas
  • Patent number: 11789826
    Abstract: A computer system includes memory configured to store software application files, and a processor configured to execute computer executable instructions. The instructions include identifying a target software application, archiving files of the target software application, and creating, in the directory, one or more replacement executable files that correspond to one or more executable files of the target software application. The instructions include detecting, by a first replacement executable file of the one or more replacement executable files, an execution call to the first replacement executable file corresponding to a first executable file of the target software application. The instructions include, in response to detection of the detected execution call, restoring files of the target software application and forwarding the detected execution call to the first executable file of the target software application in the directory to allow the first executable file to process the detected execution call.
    Type: Grant
    Filed: January 31, 2022
    Date of Patent: October 17, 2023
    Assignee: Cigna Intellectual Property, Inc.
    Inventor: Frank R. Fazio
  • Patent number: 11789610
    Abstract: A 3D-stacked memory device including: a base die including a plurality of switches to direct data flow and a plurality of arithmetic logic units (ALUs) to compute data; a plurality of memory dies stacked on the base die; and an interface to transfer signals to control the base die.
    Type: Grant
    Filed: June 21, 2021
    Date of Patent: October 17, 2023
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Mu-Tien Chang, Prasun Gera, Dimin Niu, Hongzhong Zheng
  • Patent number: 11789867
    Abstract: A data processing system includes a cache system configured to transfer data stored in the memory system to a processor and to transfer data from the processor to the memory system. The cache system comprises a cache and a data encoder associated with the cache that is configured to encode uncompressed data from the cache for storing in the memory system in a compressed format, and decode compressed data from the memory system for storing in the cache in an uncompressed format.
    Type: Grant
    Filed: January 14, 2020
    Date of Patent: October 17, 2023
    Assignee: Arm Limited
    Inventors: Olof Henrik Uhrenholt, Andreas Due Engh-Halstvedt
  • Patent number: 11789700
    Abstract: An information processing device includes: a memory; and a processor coupled to the memory, the processor being configured to: sort stream data buffered in units of wraps of a sequential recording medium, in a column order and a time order of the stream data, as primary data to be written into a primary wrap of the sequential recording medium; and control writing of the sorted primary data into the primary wrap, wherein the sorting of the stream data is configured to sort secondary data to be written into a secondary wrap that follows the primary wrap, in a reverse order of the column order and in the time order, and wherein the controlling of the primary data is configured to control writing of the sorted secondary data into the secondary wrap.
    Type: Grant
    Filed: December 16, 2020
    Date of Patent: October 17, 2023
    Assignee: FUJITSU LIMITED
    Inventor: Ken Iizawa
  • Patent number: 11789862
    Abstract: A total estimated occupancy value of a first data on a first data block of a plurality of data blocks is determined. To determine the total estimated occupancy value of the first data block, a total block power-on-time (POT) value of the first data block is determined. Then, a scaling factor is applied to the total block POT value to determine the total estimated occupancy value of the first data block. Whether the total estimated occupancy value of the first data block satisfies a threshold criterion is determined. Responsive to determining that the total estimated occupancy value of the first data block satisfies the threshold criterion, data stored at the first data block is relocated to a second data block of the plurality of data blocks.
    Type: Grant
    Filed: June 7, 2022
    Date of Patent: October 17, 2023
    Assignee: Micron Technology, Inc.
    Inventors: Kishore Kumar Muchherla, Renato C. Padilla, Sampath K. Ratnam, Saeed Sharifi Tehrani, Peter Feeley, Kevin R. Brandt
  • Patent number: 11784946
    Abstract: A processor, processor implementation method, and a storage medium are disclosed, which relates to the field of artificial intelligence and deep learning. The processor includes: a system controller a data packing and unpacking module, a storage array module, and an operation module configured to perform operation processing on the acquired first packet, generate the second packet according to the operation result data, and return the second packet to the data packing and unpacking module. The storage array module comprises N1 storage units. The data packing and unpacking module comprises N2 data packing and unpacking units, each of the data packing and unpacking units is connected to the routing and switching module through a data channel. The universal operation module comprises M operation units. The activation operation module comprises P operation unit, each of the operation units is connected to the routing and switching module through a data channel.
    Type: Grant
    Filed: August 5, 2021
    Date of Patent: October 10, 2023
    Assignee: BEIJING BAIDU NETCOM SCIENCE AND TECHNOLOGY CO., LTD.
    Inventor: Xiaoping Yan
  • Patent number: 11782639
    Abstract: Techniques for automated datastore unavailability handling are provided. In one set of embodiments, a computer system can receive a request to bring a datastore offline and, in response to the request, identify one or more virtual machines (VMs) in a virtualized computing environment that have one or more virtual disks stored in the datastore. The computer system can then, for each of the one or more VMs, determine an action to be taken with respect to the VM in response to the datastore's unavailability and trigger execution of the action.
    Type: Grant
    Filed: February 4, 2021
    Date of Patent: October 10, 2023
    Assignee: VMware, Inc.
    Inventors: Cormac Hogan, Duncan Epping, Frank Denneman
  • Patent number: 11775177
    Abstract: An apparatus (4) comprises memory access circuitry (12) to control access to data stored in a memory; and memory integrity checking circuitry (20) to verify integrity of data stored in the memory, using an integrity tree (26) in which the association between parent and child nodes is provided by a pointer. This helps to reduce the memory footprint of the tree.
    Type: Grant
    Filed: October 17, 2019
    Date of Patent: October 3, 2023
    Assignee: Arm Limited
    Inventors: Yuval Elad, Roberto Avanzi, Jason Parker
  • Patent number: 11775178
    Abstract: Apparatus, media, methods, and systems are disclosed for improved data relocation based on read-level voltages. A data storage system may include a non-volatile memory device including a source region and a destination region. The destination region may include a first destination block and a second destination block. A controller may read first data in the source region using a first read-level voltage, and read second data in the source region using a second read-level voltage. The controller may associate, based on the first and second read-level voltages, each of the first data and the second data with a respective one of the first and the second destination blocks. The controller may cause each of the first and second data to be stored in the associated one of the first and second destination blocks.
    Type: Grant
    Filed: June 23, 2021
    Date of Patent: October 3, 2023
    Assignee: WESTERN DIGITAL TECHNOLOGIES, INC.
    Inventors: Jun Tao, Niang-Chu Chen
  • Patent number: 11775436
    Abstract: One embodiment of a cache invalidation method includes storing an invalidation status usable by a computing node to identify, from a broadcast cache invalidation queue, a last processed invalidation that was processed with respect to an object cache used by the node. The method further comprises the node determining a set of unprocessed invalidations from the broadcast cache invalidation queue that are subsequent to the last processed invalidation determined from the invalidation status. The node processes the set of unprocessed invalidations to clear cached objects from the object cache. Based on processing the set of unprocessed invalidations to clear cached objects from the object cache, the invalidation status is updated with an identifier corresponding to a last invalidation from the set of previously unprocessed invalidations.
    Type: Grant
    Filed: October 25, 2021
    Date of Patent: October 3, 2023
    Assignee: Open Text SA ULC
    Inventors: Michael Gerard Jaskiewicz, Sarah Barnes Atlas, Mukesh Chowdhary, Lloyd Douglas Forrest
  • Patent number: 11768624
    Abstract: One or more techniques and/or computing devices are provided for resilient replication of storage operations. For example, a first storage controller may host first storage having a replication relationship with second storage hosted by a second storage controller. To improve resiliency against transient network issues of a network between the storage controllers, the first storage controller may implement a queue and retry mechanism to retry replication operations not acknowledge back by the second storage controller within a threshold time. The second storage controller may maintain a cumulative sequence number of a latest replication operation performed in order, an operation response map of replication operations performed out of order, and an operation finder map identifying currently implemented replication operations, which may be used to process incoming replication operations. Single write semantics, write order consistency, and reduction of write amplification may be provided.
    Type: Grant
    Filed: December 6, 2021
    Date of Patent: September 26, 2023
    Assignee: NetApp, Inc.
    Inventors: Akhil Kaushik, Anil Kumar Ponnapur, Aravind Srinivasa Raghavan, Manoj Kumar V Sundararajan