Abstract: An apparatus (4) comprises memory access circuitry (12) to control access to data stored in a memory; and memory integrity checking circuitry (20) to verify integrity of data stored in the memory, using an integrity tree (26) in which the association between parent and child nodes is provided by a pointer. This helps to reduce the memory footprint of the tree.

Abstract: Apparatus, media, methods, and systems are disclosed for improved data relocation based on read-level voltages. A data storage system may include a non-volatile memory device including a source region and a destination region. The destination region may include a first destination block and a second destination block. A controller may read first data in the source region using a first read-level voltage, and read second data in the source region using a second read-level voltage. The controller may associate, based on the first and second read-level voltages, each of the first data and the second data with a respective one of the first and the second destination blocks. The controller may cause each of the first and second data to be stored in the associated one of the first and second destination blocks.

Abstract: One embodiment of a cache invalidation method includes storing an invalidation status usable by a computing node to identify, from a broadcast cache invalidation queue, a last processed invalidation that was processed with respect to an object cache used by the node. The method further comprises the node determining a set of unprocessed invalidations from the broadcast cache invalidation queue that are subsequent to the last processed invalidation determined from the invalidation status. The node processes the set of unprocessed invalidations to clear cached objects from the object cache. Based on processing the set of unprocessed invalidations to clear cached objects from the object cache, the invalidation status is updated with an identifier corresponding to a last invalidation from the set of previously unprocessed invalidations.

Abstract: One or more techniques and/or computing devices are provided for resilient replication of storage operations. For example, a first storage controller may host first storage having a replication relationship with second storage hosted by a second storage controller. To improve resiliency against transient network issues of a network between the storage controllers, the first storage controller may implement a queue and retry mechanism to retry replication operations not acknowledge back by the second storage controller within a threshold time. The second storage controller may maintain a cumulative sequence number of a latest replication operation performed in order, an operation response map of replication operations performed out of order, and an operation finder map identifying currently implemented replication operations, which may be used to process incoming replication operations. Single write semantics, write order consistency, and reduction of write amplification may be provided.

Abstract: A system with storage memory and a processing device has a logical deletion to physical erasure time bound. The system dereferences data, responsive to a direction to delete the data. The system monitors physical blocks in storage memory for live data and the dereferenced data. The system cooperates garbage collection with monitoring the physical blocks, so that at least a physical block having the dereferenced data is garbage collected and erased within a logical deletion to physical erasure time bound.

Abstract: A method, device, and system for controlling a data read/write command in an NVMe over fabric architecture. In the method provided in the embodiments of the present disclosure, a data processing unit receives a control command sent by a control device, the data processing unit divides a storage space of a buffer unit into at least two storage spaces according to the control command sent by the control device, and establishes a correspondence between the at least two storage spaces and command queues, and after receiving a first data read/write command that is in a first command queue and that is sent by the control device, the data processing unit buffers, in a storage space that is of the buffer unit and that is corresponding to the first command queue, data to be transmitted according to the first data read/write command.

Abstract: A data merging method can copy a new logical to physical mapping table and update a copied logical to physical mapping table according to a physical address of a recycling unit expected to be written at the same time. In this way, the number of times that the same logic to physical mapping table is read multiple times during the data merging operation can be reduced to improve the execution efficiency of the data merging operation, thereby increasing the system performance of the memory storage device.

Abstract: A method and apparatus for data minoring are described. In one embodiment, a method for implementing country-specific data locality to cause data related to local transactions to be stored within the country in which the transactions occurred, comprises: capturing a set of transaction data associated with payment processing transactions into a first public cloud storage resource; and performing data mirroring across a heterogeneous set of cloud providers using a pipeline having a plurality of pipeline stages executed by one or more processors.

Abstract: The present disclosure includes apparatuses and methods related to transaction identification. An example apparatus can determine a transaction identification (TID) associated with a command by comparing a host transaction identification (TID) record with a memory device transaction identification (TID) record.

Abstract: A memory system connectable to a host includes a nonvolatile memory and a controller. The controller is configured to generate one or more virtual storage regions each of which is associated with a virtual machine running in the host, using physical memory regions of the nonvolatile memory, maintain a threshold value for each of said one or more virtual storage regions, determine a cumulative amount of data that have been written in each of said one or more virtual storage regions, and restrict writing of data with respect to a virtual storage region for which the cumulative amount exceeds the threshold value.

Abstract: In various embodiments, a write state application generates a snapshot that includes one or more data values associated with a source dataset. In operation, the write state application performs one or more compression operations on the source dataset to generate a first compressed record. The write state application then serializes the first compressed record and a second compressed record to generate a first compressed record list. Finally, the write state application generates the snapshot based on the first compressed record list. When the data values are accessed from the first snapshot, the size of the snapshot is maintained. Advantageously, because the size of the snapshot is smaller than the size of the source dataset, some consumers that are unable to store the entire source dataset in random access memory (RAM) are able to store the entire snapshot in RAM.

Abstract: A data storage method includes partitioning a data into an array having a plurality of data blocks and storing the data blocks across a plurality of storage nodes. Parity blocks are encoded based on the data array by performing a shift operation on the data array to produce a shifted array and performing an exclusive OR (XOR) operation on the elements in each row of the shifted array to produce a parity block. The method further includes storing the parity blocks across a plurality of the storage nodes. Systems are configured to recover data from a data array in the event that the data array is at least partly inaccessible.

Abstract: A storage system suspends an ongoing program operation to execute a read command. There is a limit on the number of times the storage system can suspend the program operation, and latencies occur for read commands that are received after the limit has been reached. To improve read quality of service, a blackout window is established that prevents the storage system from suspending the program operation for a period of time after the program operation resumes. The period of time can be chosen such that program suspensions are evenly distributed over the course of the program operation.

Abstract: Techniques are provided for implementing a persistent memory storage tier to manage persistent memory of a node. The persistent memory is managed by the persistent memory storage tier at a higher level within a storage operating system storage stack than a level at which a storage file system of the node is managed. The persistent memory storage tier intercepts an operation targeting the storage file system. The persistent memory storage tier retargets the operation from targeting the storage file system to targeting the persistent memory. The operation is transmitted to the persistent memory.

Abstract: A processor, processor implementation method, and a storage medium are disclosed, which relates to the field of artificial intelligence and deep learning. The processor includes: a system controller a data packing and unpacking module, a storage array module, and an operation module configured to perform operation processing on the acquired first packet, generate the second packet according to the operation result data, and return the second packet to the data packing and unpacking module. The storage array module comprises N1 storage units. The data packing and unpacking module comprises N2 data packing and unpacking units, each of the data packing and unpacking units is connected to the routing and switching module through a data channel. The universal operation module comprises M operation units. The activation operation module comprises P operation unit, each of the operation units is connected to the routing and switching module through a data channel.

Abstract: This disclosure provides techniques for managing memory which match per-data metrics to those of other data or to memory destination. In one embodiment, wear data is tracked for at least one tier of nonvolatile memory (e.g., flash memory) and a measure of data persistence (e.g., age, write frequency, etc.) is generated or tracked for each data item. Memory wear management based on these individually-generated or tracked metrics is enhanced by storing or migrating data in a manner where persistent data is stored in relatively worn memory locations (e.g., relatively more-worn flash memory) while temporary data is stored in memory that is less worn or is less susceptible to wear. Other data placement or migration techniques are also disclosed.

Abstract: A request to program a set of host data items to management units (MUs) of a fault tolerant stripe associated with a memory sub-system is received. A set of memory access operations to be executed at the MUs of the fault tolerant stripe in accordance with the received request is determined. The set of memory access operations include one or more read operations to read data from the MUs of the fault tolerant stripe. The set of memory access operations also include one or more write operations to write the set of host data items and redundancy metadata associated with the set of host data items to MUs of the fault tolerant stripe. A first series of commands corresponding to the one or more read operations of the set of memory access operations is executed. The redundancy metadata associated with the set of host data items is generated based on the data read from the MUs of the fault tolerant stripe during execution of the first series of commands and the set of host data items.

Abstract: A method includes utilizing, while delivery of power from a main power supply to a memory sub-system is interrupted, a processing device of the memory subsystem to monitor a characteristic of the memory sub-system associated with data retention at a non-volatile memory component of the memory sub-system. The method further includes utilizing, while delivery of power from a main power supply to a memory sub-system is interrupted, a processing device of the memory subsystem to predict, based on the monitored characteristic, an impending data loss event for the non-volatile memory component.

Abstract: Disclosed herein are systems having an integrated circuit device disposed within an integrated circuit package having a periphery, and within this periphery a transaction processor is configured to receive a combination of signals (e.g., using a standard memory interface), and intercept some of the signals to initiate a data transformation, and forward the other signals to one or more memory controllers within the periphery to execute standard memory access operations (e.g., with a set of DRAM devices). The DRAM devices may or may not be in within the package periphery. In some embodiments, the transaction processor can include a data plane and control plane to decode and route the combination of signals. In other embodiments, off-load engines and processor cores within the periphery can support execution and acceleration of the data transformations.

Abstract: The present disclosure provides methods, apparatuses, and systems for implementing and operating a memory module, for example, in a computing device that includes a network interface, which is coupled to a network to enable communication with a client device, and processing circuitry, which is coupled to the network interface via a data bus and programmed to perform operations based on user inputs received from the client device. The memory module includes memory devices, which may be non-volatile memory or volatile memory, and a memory controller coupled between the data bus and the of memory devices. The memory controller may be programmed to determine when the processing circuitry is expected to request a data block and control data storage in the memory devices.