Abstract: A packaged semiconductor device includes a first bond pad, a second bond pad, a first bond wire that includes a first end bonded to the first bond pad and a second end bonded to the second bond pad, and a second bond wire that includes a first end that is electrically connected to the first bond pad and a second end that is electrically connected to the second bond pad. The first end of the second bond wire is bonded to the first end of the first bond wire. A method of bonding a bond wire includes bonding a first end of a first bond wire to a contact surface of a first bond pad and bonding a first end of a second bond wire to a surface of the first end of the first bond wire.

Abstract: A semiconductor device is provided. The semiconductor device includes: a substrate with first-conductivity-type impurities; first and second active regions provided on the substrate; a first deep element isolation layer surrounding the first active region; a second deep element isolation layer surrounding the second active region; a suction region surrounding the first and second deep element isolation layers, the suction region including the first-conductivity-type impurities; a well region provided in the substrate between the first and second active regions, the well region including second-conductivity-type impurities different from the first-conductivity-type impurities; a shallow element isolation layer provided between the suction region and the well region; and a guard structure connected to the suction region. The substrate includes a signal path portion that is provided between a top surface of the substrate and the well region, and surrounds an upper portion of the well region.

Abstract: Provided are a display panel and a manufacturing method thereof, and a display device. At least one sub-pixel comprises a light emitting element; a first transistor comprising a first active layer comprising first and second electrode regions connected to data line and power line respectively; a capacitor; a second transistor comprising a second active layer; a third transistor comprising a third gate connected to a reset line, and a third active layer comprising a third channel region. Orthographic projections of the power line, the reset line, the third channel region and the data line are first, second, third and fourth projections respectively. The region of first, second, and third projections overlapping with each other is first region, and regions of first projection overlapping with second projection and not overlapping with third projection comprise a third region and a second region having an area not smaller than the third region.

Abstract: A display may include light-emitting components such as light-emitting diodes on a transparent substrate. Conductive signal paths between the light-emitting components, driver integrated circuits for controlling the light-emitting components, and the light-emitting components themselves may be opaque. To mitigate diffraction artifacts caused by the opaque components, the opaque footprint of the display may be selected to include non-periodic portions. The non-periodic portions increase randomness and reduce periodicity within the opaque footprint, which mitigates perceptible diffraction artifacts when viewing the display. One or both of the component mounting portions and interconnect portions of the opaque footprint may be non-periodic. The component mounting portions may have random shapes. The interconnect portions may follow random paths between the component mounting portions.

Abstract: Semiconductor devices and method of manufacture are provided. In embodiments a conductive connector is utilized to provide an electrical connection between a substrate and an overlying shield. The conductive connector is placed on the substrate and encapsulated with an encapsulant. Once encapsulated, an opening is formed through the encapsulant to expose a portion of the conductive connector. The shield is deposited through the encapsulant to make an electrical connection to the conductive connector.

Abstract: Provided is a method for transferring a chip, including: disposing a target substrate in a sealed chamber; applying charges of different polarities to a first alignment bonding structure of the target substrate and a first chip bonding structure of the chip, and injecting an insulation fluid flowing in a first direction into the sealed chamber, so that the first chip bonding structure is aligned with the first alignment bonding structure; applying charges of different polarities to a second alignment bonding structure of the target substrate and a second chip bonding structure of the chip, and changing the flowing direction of the insulation fluid to a second direction, so that the second chip bonding structure is aligned with the second alignment bonding structure; and applying a bonding force to the chip, so that the chip bonding structures is bonded to the alignment bonding structures.

Abstract: A semiconductor structure includes a die embedded in a molding material, the die having die connectors on a first side; a first redistribution structure at the first side of the die, the first redistribution structure being electrically coupled to the die through the die connectors; a second redistribution structure at a second side of the die opposing the first side; and a thermally conductive material in the second redistribution structure, the die being interposed between the thermally conductive material and the first redistribution structure, the thermally conductive material extending through the second redistribution structure, and the thermally conductive material being electrically isolated.

Abstract: A semiconductor chip packaging method includes forming a bump on a wafer, forming a coating film covering the bump, laser grooving the wafer, plasma etching the wafer on which the laser grooving is performed, exposing the bump by removing the coating film covering the bump, fabricating a semiconductor die by performing mechanical sawing of the wafer, and packaging the semiconductor die.

Abstract: A semiconductor device includes a first coil, a second coil, and a third coil. The second coil is disposed with respect to the first coil. The third coil is configured to sense a signal on the first coil. A first overlapped area, on a projection plane, of the third coil and the first coil is larger than a second overlapped area, on the projection plane, of the third coil and the second coil.

Abstract: A semiconductor device includes a source/drain region in a fin-type active pattern, a gate structure adjacent to the source/drain region, and an insulating layer on the source/drain region and the gate structure. A shared contact plug penetrates through the insulating layer and includes a first lower portion connected to the source/drain region, a second lower portion connected to the gate structure, and an upper portion connected to upper surfaces of the first lower portion and the second lower portion. A plug spacer film is between the insulating layer and at least one of the first lower portion and the second lower portion and includes a material different from a material of the insulating layer.

Abstract: Deep gate-all-around semiconductor devices having germanium or group 111-V active layers are described. For example, a non-planar semiconductor device includes a hetero-structure disposed above a substrate. The hetero-structure includes a hetero-junction between an upper layer and a lower layer of differing composition. An active layer is disposed above the hetero-structure and has a composition different from the upper and lower layers of the hetero-structure. A gate electrode stack is disposed on and completely surrounds a channel region of the active layer, and is disposed in a trench in the upper layer and at least partially in the lower layer of the hetero-structure. Source and drain regions are disposed in the active layer and in the upper layer, but not in the lower layer, on either side of the gate electrode stack.

Abstract: A first conductive material having a first hardness is disposed within a recess or opening of a microelectronic component, in a first preselected pattern, and forms a first portion of an interconnect structure. A second conductive material having a second hardness different from the first hardness is disposed within the recess or opening in a second preselected pattern and forms a second portion of the interconnect structure.

Abstract: The present technology includes a memory device. The memory device includes a stack structure including word lines and a select line, a vertical hole vertically penetrating the stack structure, and a memory layer, a channel layer, and a plug, sequentially formed along an inner side surface of the vertical hole. The plug includes a material layer having a fixed negative charge.

Abstract: A semiconductor device assembly is provided. The assembly includes a substrate including an upper surface having a plurality of internal contact pads and at least one grounding pad and a lower surface having a plurality of external contact pads. The assembly further includes a semiconductor die coupled to the plurality of internal contact pads, a conductive underfill dam coupled to the at least one grounding pad, and underfill material disposed at least between the semiconductor die and the substrate. The underfill material includes a fillet between the semiconductor die and the underfill dam. The assembly further includes a conductive EMI shield disposed over the semiconductor die, the fillet, and the conductive underfill dam.

Abstract: In some embodiments, a radio-frequency device can be manufactured by a method that includes forming or providing a substrate, fabricating or providing a flip chip die having a front side and a back side, and including an integrated circuit implemented on the front side, and mounting the front side of the flip chip die on the substrate. The method can further include implementing a shielding component over the back side of the flip chip die to provide electromagnetic shielding between a first region within or on the flip chip die and a second region away from the flip chip die.

Abstract: A semiconductor device includes a lower channel pattern and an upper channel pattern stacked on a substrate in a first direction perpendicular to a top surface of the substrate, lower source/drain patterns on the substrate and at a first side and a second side of the lower channel pattern, upper source/drain patterns stacked on the lower source/drain patterns and at a third side and a fourth side of the upper channel pattern, a first barrier pattern between the lower source/drain patterns and the upper source/drain patterns, and a second barrier pattern between the first barrier pattern and the upper source/drain patterns. the first barrier pattern includes a first material and the second barrier pattern includes a second material, wherein the first material and the second material are different.

Abstract: A package structure and a manufacturing method for the same are provided. The package structure includes a circuit, a mold sealing layer, a conductive metal board, and a conductive layer. The circuit board includes a substrate and a first electronic element disposed on the substrate. The mold sealing layer is disposed on the substrate and covers the first electronic element. The mold sealing layer has a top surface, a bottom surface corresponding to the top surface, and a side surface connected between the top surface and the bottom surface. The conductive metal board is disposed on the top surface and adjacent to the first electronic element. The conductive layer is disposed on the side surface and electrically connected to the conductive metal board. The conductive metal board and the conductive layer are each an independent component.

Abstract: A multifaceted capillary that can be used in a wire-bonding machine to create a multi-segment wire-bond is disclosed. The multifaceted capillary is shaped to apply added pressure and thickness to an outer segment of the multi-segment wire-bond that is closest to the wire loop. The added pressure eliminates a gap under a heel portion of the multi-segment wire-bond and the added thickness increases a mechanical strength of the heel portion. As a result, a pull test of the multi-segment wire-bond may be higher than a single-segment wire-bond and the multi-segment wire-bond may resist cracking, lifting, or breaking.

Abstract: A semiconductor device includes a sense amplifier, a first magnetic tunneling junction (MTJ) connected to the sense amplifier at a first distance, a second MTJ connected to the sense amplifier at a second distance, and a third MTJ connected to the sense amplifier at a third distance. Preferably, the first distance is less than the second distance, the second distance is less than the third distance, a critical dimension of the first MTJ is less than a critical dimension of the second MTJ, and the critical dimension of the second MTJ is less than a critical dimension of the third MTJ.

Abstract: An organic light emitting display device including a light extraction reduction preventing layer disposed between a display unit disposed on a substrate and an encapsulation layer for protecting the display unit, which improves light emission efficiency by reducing an amount of light dissipating while light generated from an emission layer of the display unit is extracted to the outside.