Abstract: In certain embodiments, a semiconductor device includes a substrate having an n-doped well feature and an epitaxial silicon germanium fin formed over the n-doped well feature. The epitaxial silicon germanium fin has a lower part and an upper part. The lower part has a lower germanium content than the upper part. A channel is formed from the epitaxial silicon germanium fin. A gate is formed over the epitaxial silicon germanium fin. A doped source-drain is formed proximate the channel.

Abstract: Embodiments of 3D memory devices and methods for forming the same are disclosed. In an example, a method for forming a 3D memory device is disclosed. A channel opening extending vertically is formed above a substrate. A semiconductor plug is formed in a lower portion of the channel opening. A memory film and a channel sacrificial layer are subsequently formed above the semiconductor plug and along a sidewall of the channel opening. A semiconductor plug protrusion protruding above the semiconductor plug and through a bottom of the memory film and the channel sacrificial layer is formed. A cap layer is formed in the channel opening and over the channel sacrificial layer. The cap layer covers the semiconductor plug protrusion. A semiconductor channel is formed between the memory film and the cap layer by replacing the channel sacrificial layer with a semiconductor material epitaxially grown from the semiconductor plug protrusion.

Abstract: A semiconductor device includes first and second members. In the first member, a first electronic circuit including a semiconductor element is formed. The second member is joined to an area of part of a first surface of the first member, and includes a second electronic circuit including a semiconductor element formed of a semiconductor material different from that of the semiconductor element of the first electronic circuit. An interlayer insulating film covers the second member and an area of the first surface of the first member to which the second member is not joined. An inter-member connection wire on the interlayer insulating film couples the first and second electronic circuits through an opening in the interlayer insulating film. A shield structure including a first metal pattern disposed on the interlayer insulating film shields a shielded circuit, which is part of the first electronic circuit, in terms of radio frequencies.

Abstract: A method for evaluation of thin film non-uniform stress using high order wafer warpage, the steps including measuring a net wafer warpage across a wafer area due to thin film deposition, fitting a two dimensional low-order polynomial to the wafer warpage measurements and subtracting the low-order polynomial from the net wafer warpage across the wafer area.

Abstract: A light emitting stacked structure including a first epitaxial stack including a first n-type semiconductor layer, a first p-type semiconductor layer, and a first active layer disposed therebetween, a second epitaxial stack disposed on the first epitaxial stack and including a second n-type semiconductor layer, a second p-type semiconductor layer, and a second active layer disposed therebetween, a third epitaxial stack disposed on the second epitaxial layer and including a third n-type semiconductor layer, a third p-type semiconductor layer, and a third active layer disposed therebetween, and a shared electrode disposed between two adjacent epitaxial stacks facing each other, in which two semiconductor layers of the two adjacent epitaxial stacks with the shared electrode therebetween have a same polarity.

Abstract: Embodiments of 3D memory devices and methods for forming the same are disclosed. In an example, a 3D memory device includes a substrate, a memory stack including interleaved conductive layers and dielectric layers above the substrate, and a channel structure extending vertically through the memory stack. The channel structure includes a high dielectric constant (high-k) dielectric layer disposed continuously along a sidewall of the channel structure, a memory film over the high-k dielectric layer along the sidewall of the channel structure, and a semiconductor channel over the memory film along the sidewall of the channel structure.

Abstract: A semiconductor package structure and a method of manufacturing the same are provided. The semiconductor package structure includes a first electronic component, a second electronic component, and a reinforcement component. The reinforcement component is disposed above the first electronic component and the second electronic component. The reinforcement component is configured to reduce warpage.

Abstract: A quantum device (100) includes an interposer (112), a quantum chip (111) mounted on the interposer (112), and a shield part (150) provided so as to surround a quantum circuit region of the interposer (112) and the quantum chip (111). Accordingly, the quantum device (100) is able to prevent interference in the quantum circuit region due to exogenous noise.

Abstract: A semiconductor device includes a semiconductor chip including an electrical contact arranged on a main surface of the semiconductor chip, an external connection element configured to provide a first electrical connection between the semiconductor device and a printed circuit board, and an electrical redistribution layer extending in a direction parallel to the main surface of the semiconductor chip and configured to provide a second electrical connection between the electrical contact of the semiconductor chip and the external connection element. The electrical redistribution layer includes a ground line connected to a ground potential and a signal line configured to carry an electrical signal having a wavelength.

Abstract: Provided is a display device including a substrate including a display area including a plurality of pixel areas, and a non-display area outside the display area, a pixel circuit layer including a plurality of circuit elements in the display area, a display element layer including a plurality of light-emitting elements in the display area on the pixel circuit layer, and first and second alignment lines on the substrate, and each including a main line at the same layer as at least one electrode on the display element layer, and a sub line electrically connected to the main line and at the same layer as at least one electrode on the pixel circuit layer, wherein the first alignment line and the second alignment line do not include the main line in the non-display area, and include the sub line to be spaced apart from one edge of the substrate.

Abstract: A semiconductor device according to an embodiment includes a stacked body having first films and second films that are alternately stacked, a light shielding film provided in a specific layer of the stacked body and having a higher optical absorptivity than that of the second films, and a channel film extending in the stacked body in the stacking direction. The channel film includes a first part located on an upper side than the light shielding film in the stacking direction and containing a monocrystalline semiconductor.

Abstract: A micro device includes a securing layer, a plurality of micro device units that are separated from each other and that are spaced apart from the securing layer, and a connecting layer that interconnects the micro device units in at least one group of two or more and that is connected to the securing layer so that the micro device units are connected to the securing layer through the connecting layer. A method of making the micro device is also provided.

Abstract: The disclosure provides an electronic device, which includes a substrate, two adjacent pixels, a first scan line, and two adjacent light shielding layers. The two adjacent pixels are disposed on the substrate and arranged along the first direction. A first pixel of the two adjacent pixels includes a first sub-pixel, and the first sub-pixel includes a first active region and a first conductive element electrically connected to the first active region. The first scan line is extending along the first direction. The two adjacent light shielding layers are respectively disposed between the two adjacent pixels and the substrate. The two adjacent light shielding layers are spaced apart by a first gap region, and the first gap region overlaps the first conductive element. The display device of the disclosure can reduce the problem of image quality degradation caused by photo-leakage current.

Abstract: Disclosed is a cost-effective method to fabricate a multifunctional collimator structure for contact image sensors to filter ambient infrared light to reduce noises. In one embodiment, an optical collimator, includes: a dielectric layer; a substrate; a plurality of via holes; and a conductive layer, wherein the dielectric layer is formed over the substrate, wherein the plurality of via holes are configured as an array along a lateral direction of a first surface of the dielectric layer, wherein each of the plurality of via holes extends through the dielectric layer and the substrate from the first surface of the dielectric layer to a second surface of the substrate in a vertical direction.

Abstract: Methods for forming semiconductor structures are provided. The method includes forming a fin structure over a substrate and forming a dummy gate structure across the fin structure. The method further includes forming a spacer layer on a sidewall of the fin structure at a source/drain region. The method further includes removing at least a portion of the spacer layer to enlarge the source/drain region and forming a source/drain structure in the source/drain region.

Abstract: According to one embodiment, a semiconductor device includes a memory region and a peripheral circuit region, the peripheral circuit region includes a first region and a second region outside of the first region. The semiconductor device includes, in the first region, a transistor including a gate insulating layer and a gate structure that includes a gate electrode. A first structure is in the second region and includes a first insulating layer and a dummy gate electrode on the first insulating layer. The first insulating layer has a side surface facing outward from the peripheral circuit region and a second insulating layer that covers the first side surface and is an insulating material other than a silicon oxide.

Abstract: Systems and methods are provided for fabricating a semiconductor device structure. An example semiconductor device structure includes a first device layer, a second device layer and an inter-level connection structure. The first device layer includes a first conductive layer and a first dielectric layer formed on the first conductive layer, the first device layer being formed on a substrate. The second device layer includes a second conductive layer, the second device layer being formed on the first device layer. The inter-level connection structure includes one or more conductive materials and configured to electrically connect to the first conductive layer and the second conductive layer, the inter-level connection structure penetrating at least part of the first dielectric layer. The first conductive layer is configured to electrically connect to a first electrode structure of a first semiconductor device within the first device layer.

Abstract: In a display device including a pixel arranged therein, the pixel including a light emitting unit in which an anode electrode is formed in the uppermost layer of a multilayer wiring structure formed by alternately stacking a plurality of insulating layers and a plurality of wiring layers, and a capacitor element electrically connected to the anode electrode of the light emitting unit, or in an electronic device including the display device, the capacitor element including a first electrode formed in a wiring layer below the anode electrode, a second electrode formed opposite to the first electrode, and attached to the anode electrode of the light emitting unit via a conductive rib, and a first insulating layer interposed between the first electrode and the second electrode.

Abstract: An alternating stack of insulating layers and electrically conductive layers, a retro-stepped dielectric material portion overlying stepped surfaces of the alternating stack, and memory stack structures extending through the alternating stack are formed over a substrate. A patterned etch mask layer including discrete openings is formed thereabove. Via cavities through an upper region of the retro-stepped dielectric material portion by performing a first anisotropic etch process. Metal plates are selectively formed on physically exposed surfaces of a first subset of the electrically conductive layers by a selective metal deposition process. A subset of the via cavities without any metal plates therein are vertically extended downward by performing a second anisotropic etch process while the metal plates protect underlying electrically conductive layers. Via cavities can be formed without punching through electrically conductive layers.

Abstract: A display device includes a substrate, a circuit element layer on the substrate, a display element layer on the circuit element layer, a sealing film on the display element layer, an oxide film on the sealing film, a barrier metal layer on the oxide film, and a wiring layer on the barrier metal layer, wherein a surface of the sealing film in contact with the oxide film has concave/convexities, and the barrier metal layer is formed by titanium nitride. A height of the concave/convexities of the surface of the sealing film may be less than 30 nm. A thickness of the oxide film may be 5 nm or less.