Abstract: Provided is a semiconductor device of the embodiment including: an oxide semiconductor layer; a gate electrode; a first electrode electrically connected to one portion of the oxide semiconductor layer, the first electrode including a first region, second region, a third region, and a fourth region, the first region disposed between the first portion and the second region, the first region disposed between the third region and the fourth region, the first region containing at least one element of In, Zn, Sn or Cd, and oxygen, the second region containing at least one metal element of Ti, Ta, W, or Ru, the third region and the fourth region containing the at least one metal element and oxygen, the third region and the fourth region having an atomic concentration of oxygen higher than that of the second region; and a second electrode electrically connected to another portion of the oxide semiconductor layer.

Abstract: A semiconductor device includes a substrate having an insulating surface; a light-transmitting first electrode provided over the substrate; a light-transmitting second electrode provided over the substrate; a light-transmitting semiconductor layer provided so as to be electrically connected to the first electrode and the second electrode; a first wiring electrically connected to the first electrode; an insulating layer provided so as to cover at least the semiconductor layer; a light-transmitting third electrode provided over the insulating layer in a region overlapping with the semiconductor layer; and a second wiring electrically connected to the third electrode.

Abstract: Implementations of semiconductor packages may include a first substrate having two or more die coupled to a first side, a clip coupled to each of the two or more die on the first substrate and a second substrate having two or more die coupled to a first side of the second substrate. A clip may be coupled to each of the two or more die on the second substrate. The package may include a lead frame between the first substrate and the second substrate and a molding compound. A second side of each of the first substrate and the second substrate may be exposed through the molding compound. A perimeter of the first substrate and a perimeter of the second substrate may not fully overlap when coupled through the lead frame.

Abstract: Implementations of semiconductor packages may include a first substrate having two or more die coupled to a first side, a clip coupled to each of the two or more die on the first substrate and a second substrate having two or more die coupled to a first side of the second substrate. A clip may be coupled to each of the two or more die on the second substrate. The package may include a lead frame between the first substrate and the second substrate and a molding compound. A second side of each of the first substrate and the second substrate may be exposed through the molding compound. A perimeter of the first substrate and a perimeter of the second substrate may not fully overlap when coupled through the lead frame.

Abstract: A package-embedded board includes: a core layer having a through-hole portion; a package at least partially disposed in the through-hole portion and including a die pad, an electronic component disposed on the die pad, and a molded portion covering the electronic component; and a core insulating material disposed in the through-hole portion and covering the core layer and the package.

Abstract: Disclosed herein are integrated circuit (IC) package lids with polymer features, as well as related methods and devices. For example, in some embodiments, an IC package may include a package substrate, a lid, and a die between the package substrate and the lid. A foot or rib of the lid may include a polymer material.

Abstract: A capacitor includes: a plurality of bottom electrodes; a dielectric layer formed over the bottom electrodes; and a top electrode formed over the dielectric layer, wherein the top electrode includes a carbon-containing material and a germanium-containing material that fill a gap between the bottom electrodes.

Abstract: An optical module includes an optoelectronic assembly and a heat spreader. The optoelectronic assembly includes a flat, rigid substrate, an array of electrical contacts positioned on a first portion of the substrate, and an optoelectronics assemblage that is electrically connected to the array of contacts and is positioned apart from the array of electrical contacts. The heat spreader is comprised of a thermally conductive material and comprises a second portion that is structurally connected to the first portion and a third portion that is thermally connected to the optoelectronics assemblage.

Abstract: A wavelength conversion component includes a plurality of semiconductor multilayer film segments, a first member arranged between adjacent ones of the semiconductor multilayer film segments, and a substrate disposed above the plurality of semiconductor multilayer film segments, the substrate defining a groove.

Abstract: An ESD protection device may include: a first vertically integrated ESD protection structure comprising a first semiconductor portion, a first contact region disposed on a first side of the first semiconductor portion and a first terminal exposed on a second side of the first semiconductor portion opposite the first side of the first semiconductor portion, a second vertically integrated ESD protection structure comprising a second semiconductor portion, a second contact region disposed on a first side of the second semiconductor portion and a second terminal exposed on a second side of the second semiconductor portion opposite the first side of the second semiconductor portion, an electrical connection layer, wherein the first vertically integrated ESD protection structure and the second vertically integrated ESD protection structure are disposed on the electrical connection layer laterally separated from each other and are electrically connected with each other anti-serially via the electrical connection lay

Abstract: A manufacturing method of a semiconductor structure is disclosed, which includes: an initial structure is provided; a filling layer covering a spacer is formed on the initial structure; a filling layer with a first preset thickness is removed at a high first etching rate through a first etching process, then a filling layer with a second preset thickness is removed at a low second etching rate through a second etching process, and the partial spacer is exposed; and the filling layer and the spacer are patterned.

Abstract: A semiconductor device includes: a semiconductor substrate having opposing first and second main surfaces; a plurality of transistor cells each including a source region, a drift zone, a body region separating the source region from the drift zone, a field plate trench extending into the drift zone and including a field plate, and a planar gate on the first main surface and configured to control current through a channel of the body region; a drain region at the second main surface; and a diffusion barrier structure including alternating layers of Si and oxygen-doped Si and a Si capping layer on the alternating layers of Si and oxygen-doped Si. The diffusion barrier structure may be interposed between body regions of adjacent transistor cells and/or extend along the channel of each transistor cell and/or vertically extend in the semiconductor substrate between adjacent field plate trenches.

Abstract: Implementations of semiconductor packages may include: a first substrate having two or more die coupled to a first side, a clip coupled to each of the two or more die on the first substrate and a second substrate having two or more die coupled to a first side of the second substrate. A clip may be coupled to each of the two or more die on the second substrate. The package may include two or more spacers coupled to the first side of the first substrate and a lead frame between the first substrate and the second substrate and a molding compound. A second side of each of the first substrate and the second substrate may be exposed through the molding compound. A perimeter of the first substrate and a perimeter of the second substrate may not fully overlap when coupled through the two or more spacers.

Abstract: A semiconductor module includes a ceramic board, a circuit pattern metal plate on a principal surface of the ceramic board, and an external connection terminal including a bonding portion and a conductive portion. The metal plate includes a bonding area at a first surface thereof, and a stress relaxation portion disposed within the bonding area. The bonding portion has a bonding surface, and an edge that is located at a position overlapping an area in which the stress relaxation portion is disposed in a plan view. A solder is disposed between the bonding surface and the bonding area, to bond the external connection terminal to the circuit pattern metal plate.

Abstract: A semiconductor device package includes a substrate and a conductive lid. The conductive lid is disposed within the substrate. The conductive lid defines a waveguide having a cavity. The waveguide is configured to transmit a signal from a first electronic component to a second electronic component through the cavity.

Abstract: Implementations of semiconductor packages may include: a first substrate having two or more die coupled to a first side, a clip coupled to each of the two or more die on the first substrate and a second substrate having two or more die coupled to a first side of the second substrate. A clip may be coupled to each of the two or more die on the second substrate. The package may include two or more spacers coupled to the first side of the first substrate and a lead frame between the first substrate and the second substrate and a molding compound. A second side of each of the first substrate and the second substrate may be exposed through the molding compound. A perimeter of the first substrate and a perimeter of the second substrate may not fully overlap when coupled through the two or more spacers.

Abstract: An electronic structure includes offset three-dimensional stacked chips; and a two-piece lid structure configured to extract heat from the bottom and top of the stacked chips.

Abstract: Disclosed herein are microelectronic structures including bridges, as well as related assemblies and methods. In some embodiments, a microelectronic structure may include a substrate and a bridge.

Abstract: An electronic device includes a substrate, a dielectric spacer, a semiconductor die, and a package structure. The substrate has a dielectric layer, a die pad, first and second leads, a conductive via, and a conductive trace, the dielectric layer has an opening extending into a side, the die pad is coupled to the first lead, the second lead is coupled to the conductive via, and the conductive trace is coupled to the via. The dielectric spacer is mounted above the die pad in the opening, and the semiconductor die is mounted above the dielectric spacer, the semiconductor die includes a temperature sensor, and an electrical connection couples the semiconductor die to the conductive trace. The package structure extends on the side of the dielectric layer, on the semiconductor die, and on the conductive trace, the package structure extending around the dielectric spacer and to the die pad in the opening.

Abstract: A clip, a semiconductor package, and a method are disclosed. In one example the clip includes a die attach portion having a first main face and a second main face opposite to the first main face, and at least one through-hole extending between the first and second main faces and including a curved transition from an inner wall of the at least one through-hole to the first main face.