Abstract: A nonvolatile memory device is provided. The nonvolatile memory device comprises an active region surrounded by an isolation structure. A floating gate may be arranged over the active region, the floating gate having a first end and a second end over the isolation structure. A first doped region may be provided in the active region adjacent to a first side of the floating gate and a second doped region may be provided in the active region adjacent to a second side of the floating gate. A first capacitor may be provided over the floating gate, whereby a first electrode of the first capacitor is electrically coupled to the floating gate. A second capacitor may be provided, whereby a first electrode of the second capacitor is over the isolation structure and adjacent to the floating gate.

Abstract: An image sensing device is disclosed. The image sensing device includes a semiconductor substrate configured to generate charge carriers in response to light incident, a plurality of control regions supported by the semiconductor substrate and configured to cause majority carrier currents in the semiconductor substrate to control movement of minority carriers, and a plurality of detection regions formed adjacent to the control regions and configured to capture the minority carriers moving in the semiconductor substrate. Each of the control regions includes an upper portion, a lower portion, and a middle portion disposed between the upper portion and the lower portion. The middle portion has a smaller horizontal cross-sectional profile than each of the upper portion and the lower portion.

Abstract: Disclosed herein are via-trace structures with improved alignment, and related package substrates, packages, and computing device. For example, in some embodiments, a package substrate may include a conductive trace, and a conductive via in contact with the conductive trace. The alignment offset between the conductive trace and the conductive via may be less than 10 microns, and conductive trace may have a bell-shaped cross-section or the conductive via may have a flared shape.

Abstract: A heat dissipation structure includes a heat dissipation portion and a heat storage portion. The heat dissipation portion has the heat receiving surface including the contact surface in contact with the semiconductor generating the heat, and dissipates the heat of the semiconductor in contact with the contact surface. The heat storage portion is arranged to sandwich the semiconductor. The heat storage portion has, for example, the heat storage opening portion in which the semiconductor is positioned, and surrounds the semiconductor. The heat storage portion is provided to he in contact with the heat receiving surface, and stores the heat of the semiconductor conducted through the heat dissipation portion.

Abstract: A three-dimensional memory device includes an alternating stack of insulating layers and electrically conductive layers, memory opening fill structures extending through the alternating stack, where each of the memory opening fill structures includes a vertical semiconductor channel, a tunneling dielectric layer, and a vertical stack of memory elements located at levels of the electrically conductive layers between a respective vertically neighboring pair of the insulating layers. Each of the memory elements is located at a level of a respective one of the electrically conductive layers between the respective vertically neighboring pair of the insulating layers. Each of the memory elements includes a first memory material portion, and a second memory material portion that is vertically spaced from the first memory material portion. The second memory material portion has a different material composition from the first memory material portion.

Abstract: A semiconductor package structure is provided. The semiconductor package structure includes a substrate, a semiconductor die, a molding material, a first bonding layer, and a thermal interface material. The semiconductor die is disposed over the substrate. The molding material surrounds the semiconductor die. The first bonding layer is disposed over the semiconductor die. The thermal interface material is disposed over the molding material.

Abstract: A semiconductor device package structure is provided. The semiconductor device package structure includes a substrate having a first layer over a second layer. The first layer may have greater thermal conductivity than the second layer. The semiconductor device package structure further includes one or more dies coupled to the substrate. A heat spreader may have a first section coupled to a first surface of a first die of the one or more dies, and a second section coupled to the first layer.

Abstract: Solid state switching device including: a pair of line terminals including first and second line terminals for electrical connection with a corresponding phase conductor of an electric line; a switching assembly including one or more solid state power switches, the switching assembly having a first and second power terminals electrically connected with the first and second lines terminals, respectively; a heat sink element in thermal coupling with the switching assembly to adsorb heat from the switching assembly; an additional heat extraction arrangement to extract heat from the switching assembly and convey at least a portion of the adsorbed heat along the phase conductor through the first and second line terminals.

Abstract: A TFT backplane and a micro-LED display are provided A metal light shielding layer is placed at the lower surface of the substrate and the position of the metal light shield layer is corresponding to the active layer. This reduces the size of the side frame, which is used when assembling multiple displays in a large-size micro LED display application. This could meet the demand of large-size micro-LED display. In addition, this could further reduce the steps of depositing and patterning a conventional shield metal layer in a convention process of manufacturing the TFT. Therefore, the manufacturing steps of the TFT backplane are simplified and thus the manufacturing cost is reduced.

Abstract: A semiconductor-on-insulator (SOI) transistor includes a semiconductor layer situated over a buried oxide layer, the buried oxide layer being situated over a substrate. The SOI transistor is situated in the semiconductor layer and includes a transistor body, gate fingers, source regions, and drain regions. The transistor body has a first conductivity type. The source regions and the drain regions have a second conductivity type opposite to the first conductivity type. A heavily-doped body-implant region has the first conductivity type and overlaps at least one source region. A common silicided region electrically ties the heavily-doped body-implant region to the at least one source region. The common silicided region can include a source silicided region, and a body tie silicided region situated over the heavily-doped body-implant region. The source silicided region can be separated from a drain silicided region by the gate fingers.

Abstract: An electronic component, or a precursor thereof, that comprises a curable organopolysiloxane composition or a cured product thereof is disclosed. The curable organopolysiloxane composition is generally curable through a hydrosilylation reaction and can be applied to at least one area by a microdroplet application device. The curable organopolysiloxane composition has a viscosity of no more than 2.0 Pa·s at a strain rate of 1,000 (1/s), and a viscosity at a strain rate of 0.1 (1/s) being a value no less than 50.0 times the viscosity at a strain rate of 1,000 (1/s). In particular, the area of application generally is a substantially circular area that fits within a frame no more than 1000 ?m in diameter, a linear area no more than 1000 ?m in line width, or a pattern configured from a combination of these areas.

Abstract: A template for growing Group III-nitride semiconductor layers, a Group III-nitride semiconductor light emitting device and methods of manufacturing the same are provided. The template for growing Group III-nitride semiconductor layers includes a growth substrate having a first plane, a second plane opposite to the first plane and a groove extending inwards the growth substrate from the first plane, an insert for heat dissipation placed and secured in the groove, and a nucleation layer formed on a partially removed portion of the first plane.

Abstract: A quantum processor includes: a first chip comprising a qubit array, in which a plurality of qubits within the qubit array define an enclosed region on the first chip, in which each qubit of the plurality of qubits that define the enclosed region is arranged to directly electromagnetically couple to an adjacent qubit of the plurality of qubits that define the enclosed region, and in which each qubit of the qubit array comprises at least two superconductor islands, and a second chip bonded to the first chip, the second chip including one or more qubit control elements, in which the qubit control elements are positioned directly over the enclosed region of the first chip.

Abstract: A chip scale package structure of heat-dissipating type is provided and includes a board, a die fixed on and electrically coupled to the board, a thermally conductive adhesive sheet adhered to the die, and a package body formed on the board. The die has a heat-output surface arranged away from the board. The thermally conductive adhesive sheet is connected to at least 50% of an area of the heat-output surface. The package body covers and is connected to the die and entire of the surrounding lateral surface of the thermally conductive adhesive sheet. The die is embedded in the board, the thermally conductive adhesive sheet, and the package body. The heat-dissipating surface of the thermally conductive adhesive sheet is exposed from the package body, and a thermal conductivity of the thermally conductive adhesive sheet is at least 150% of a thermal conductivity of the package body.

Abstract: A system and method for a Laterally Diffused Metal Oxide Semiconductor (LDMOS) with Shallow Trench Isolation (STI) in the backgate region of FET with trench contacts is provided. The backgate diffusion region of the FET is split in the middle of the source-backgate side of the LDMOS with a strip of STI. A contact can be drawn across STI strip. The contact etch can be etched through the STI fill. The contact barrier material and trench fill processes can create a metal-semiconductor contact in the outline of the STI.

Abstract: A method for manufacturing a trench gate device includes: forming a trench in a substrate with a super junction structure; forming a gate dielectric layer in the trench; forming a polysilicon gate by filling a portion of the trench with polysilicon; forming an intermediate dielectric layer in the trench; forming an auxiliary polysilicon layer by filling a gap in the trench with polysilicon; forming a source region of the trench gate device in the substrate; depositing an interlayer dielectric layer, and forming contacts in the interlayer dielectric layer, wherein the polysilicon gate, the auxiliary polysilicon layer, and the source region are led out from the contacts; and connecting the led-out auxiliary polysilicon layer to the led-out source region.

Abstract: There is provided a light emitting device including: a substrate; a laminated structure provided on the substrate and having a plurality of columnar portions, in which the columnar portion includes an n-type first semiconductor layer, a p-type second semiconductor layer, a light emitting layer provided between the first semiconductor layer and the second semiconductor layer, and a third semiconductor layer having a band gap larger than that of the light emitting layer, and the third semiconductor layer includes a first part provided between the light emitting layer and the second semiconductor layer, and a second part that is in contact with a side surface of the light emitting layer.

Abstract: Provided is a semiconductor device of the embodiment including: an oxide semiconductor layer; a gate electrode; a first electrode electrically connected to one portion of the oxide semiconductor layer, the first electrode including a first region, second region, a third region, and a fourth region, the first region disposed between the first portion and the second region, the first region disposed between the third region and the fourth region, the first region containing at least one element of In, Zn, Sn or Cd, and oxygen, the second region containing at least one metal element of Ti, Ta, W, or Ru, the third region and the fourth region containing the at least one metal element and oxygen, the third region and the fourth region having an atomic concentration of oxygen higher than that of the second region; and a second electrode electrically connected to another portion of the oxide semiconductor layer.

Abstract: In a semiconductor device, a first lead frame and a second lead frame are fixed to a metal conductor base by an organic insulating film made of a polyimide-based material. The organic insulating film satisfies relationships of tpress1>tcast1 and tpress2>tcast1, where tpress1 is a thickness of a portion of the organic insulating film sandwiched between the metal conductor base and the first lead frame, tpress2 is a thickness of a portion of the organic insulating film sandwiched between the metal conductor base and the second lead frame, and tcast1 is a thickness of a portion of the organic insulating film that is not sandwiched between the metal conductor base and the first lead frame and is not sandwiched between the metal conductor base and the second lead frame.

Abstract: A three-dimensional memory device includes an alternating stack of insulating layers and electrically conductive layers located over a substrate, memory stack structures extending through the alternating stack. Each of the memory stack structures includes a vertical semiconductor channel, a tunneling dielectric layer, and a vertical stack of memory elements located at levels of the electrically conductive layers between a respective vertically neighboring pair of the insulating layers. Each of the memory elements includes a first memory material portion, and a second memory material portion that is vertically spaced from and is electrically isolated from the first memory material portion by at least one blocking dielectric material portion.