Abstract: Implementations of semiconductor packages may include a first substrate having two or more die coupled to a first side, a clip coupled to each of the two or more die on the first substrate and a second substrate having two or more die coupled to a first side of the second substrate. A clip may be coupled to each of the two or more die on the second substrate. The package may include a lead frame between the first substrate and the second substrate and a molding compound. A second side of each of the first substrate and the second substrate may be exposed through the molding compound. A perimeter of the first substrate and a perimeter of the second substrate may not fully overlap when coupled through the lead frame.

Abstract: An electronic device is disclosed. In an embodiment an electronic device includes at least one first carrier and at least one semiconductor chip, wherein the first carrier has a cavity in which the semiconductor chip is arranged.

Abstract: Implementations of semiconductor packages may include: a first substrate having two or more die coupled to a first side, a clip coupled to each of the two or more die on the first substrate and a second substrate having two or more die coupled to a first side of the second substrate. A clip may be coupled to each of the two or more die on the second substrate. The package may include two or more spacers coupled to the first side of the first substrate and a lead frame between the first substrate and the second substrate and a molding compound. A second side of each of the first substrate and the second substrate may be exposed through the molding compound. A perimeter of the first substrate and a perimeter of the second substrate may not fully overlap when coupled through the two or more spacers.

Abstract: A reliable semiconductor device is provided. The semiconductor device includes at least one die. The at least one die includes an integrated circuit region, a first recess region surrounding the integrated circuit region, and a second recess region surrounding the first recess region. A first recess is disposed in the first recess region and a second recess is disposed in the second recess region.

Abstract: An avalanche-protected field effect transistor includes, within a semiconductor substrate, a body semiconductor layer and a doped body contact region having a doping of a first conductivity type, and a source region a drain region having a doping of a second conductivity type. A buried first-conductivity-type well may be located within the semiconductor substrate. The buried first-conductivity-type well underlies, and has an areal overlap in a plan view with, the drain region, and is vertically spaced apart from the drain region, and has a higher atomic concentration of dopants of the first conductivity type than the body semiconductor layer. The configuration of the field effect transistor induces more than 90% of impact ionization electrical charges during avalanche breakdown to flow from the source region, to pass through the buried first-conductivity-type well, and to impinge on a bottom surface of the drain region.

Abstract: Disclosed are a display apparatus and a method of manufacturing the same. The display apparatus includes a light emitting part including a plurality of light emitting diodes; and a thin film transistor (TFT) panel part configured to drive the plurality of light emitting diodes. The plurality of light emitting diodes are electrically connected to the plurality of TFTs, respectively, by a layer disposed between the light emitting diode part and the TFT panel part.

Abstract: A wavelength conversion component includes a plurality of wavelength conversion members, a plurality of transmission type optical members respectively disposed on the wavelength conversion members, and a first member including a plurality of wall portions respectively located between adjacent ones of the wavelength conversion members. A light emitting device includes such wavelength conversion component.

Abstract: A transistor having: a semiconductor; a first electrode in contact with the semiconductor; a second electrode in contact with the semiconductor; and a control electrode, disposed between the first electrode and the second electrode, for controlling a flow of carriers in a channel in the semiconductor between the first electrode and the second electrode. A first electric field is produced in the channel in response to an electrical voltage applied between the first electrode and the second electrode. A field plate, comprising a resistive material, is disposed over the channel. A voltage source is connected across portions of the resistive field plate material for producing second electric field across such portions of the resistor, such second electric field being coupled into the channel to modify one or more peaks of the first electric field in the channel.

Abstract: A light emitting device includes a light emitting element, a wavelength conversion member, a reflecting member and a covering member. The light emitting element has a top surface and lateral surfaces. The wavelength conversion member has a top surface, a bottom surface, and lateral surfaces, with the bottom surface of the wavelength conversion member facing the top surface of the light emitting element. The reflecting member surrounds the lateral surfaces of the light emitting element and the lateral surfaces of the wavelength conversion member. The reflecting member has a top surface. The covering member covers the top surface of the wavelength conversion member and the top surface of the reflecting member. The covering member contains a pigment or a dye so that a body color of the covering member is the same or a similar color as a body color of the wavelength conversion member.

Abstract: A semiconductor device is provided. The semiconductor device includes a substrate, a first well, a second well, an isolation structure, a first field plate, a gate structure, a drain structure, and a source structure. The first well and the second well adjoin each other. The first well and the second well are disposed in the substrate. The isolation structure is disposed on the first well. The first field plate is disposed on the isolation structure. The gate structure crosses the first well and the second well, and an opening is defined between the first field plate and the gate structure to expose an edge of the isolation structure adjacent to the gate structure. The drain structure is disposed in the first well. The source structure is disposed in the second well.

Abstract: The present invention provides a hermetic package, including a ceramic base and a glass cover hermetically integrated with each other via a sealing material layer, wherein the ceramic base includes 0.1 mass % to 10 mass % of a black pigment, and wherein a difference between: a light absorption rate of the ceramic base at a wavelength of 808 nm when converted to 0.5 mm; and a light absorption rate of the sealing material layer at a wavelength of 808 nm when converted to 0.005 mm is 30% or less.

Abstract: An organic EL display device according to an embodiment of the present invention includes a substrate on which a display region including a plurality of pixels including an organic EL layer and an external region that surrounds the display region are formed, at least one separating wall that is formed at a part of the external region on the substrate, and an organic layer that covers at least a part of the display region, includes an organic material, and is formed on a display region side of the at least one separating wall. A wall surface of the display region side of the at least one separating wall includes an inclined surface that is inclined toward the display region side as it is extended away from the substrate.

Abstract: Provided is an integrated fan-out (InFO) package structure including a first die, a second die, a third die, a protective layer, and an interconnect structure. The first die has a first surface and a second surface opposite to each other. The first die has a plurality of through substrate vias (TSVs) protruding from the second surface. The second die and the third die are bonded on the first surface of the first die. The protective layer laterally surrounds protrusions of the plurality of TSVs that protrude from the second surface. The interconnect structure are disposed on the protective layer and electrically connected to the plurality of TSVs. The interconnect structure includes a polymer layer covering the protective layer.

Abstract: A device including an organic light emitting diode and a dielectric layer is provided. The dielectric layer provides additional distance between a reflector and the organic emission region, leading to improved reduction in non-emissive modes and enhanced efficiency.

Abstract: An LDMOS transistor and a method for manufacturing the same are provided. The method includes: forming an epitaxial layer on a substrate, forming a gate structure on an upper surface of the epitaxial layer, forming a body region and a drift region in the epitaxial layer, forming a source region in the body region, forming a first insulating layer on the gate structure and an upper surface of the epitaxial layer and, forming a shield conductor layer on the first insulating layer, forming a second insulating layer covering the shield conductor layer, forming a first conductive path, to connect the source region with the substrate, and forming a drain region in the drift region. By forming the first conductive path which connects the source region with the substrate, the size of the LDMOS transistor and the resistance can be reduced.

Abstract: A solid-state imaging device includes a photoelectric conversion section which is disposed on a semiconductor substrate and which photoelectrically converts incident light into signal charges, a pixel transistor section which is disposed on the semiconductor substrate and which converts signal charges read out from the photoelectric conversion section into a voltage, and an element isolation region which is disposed on the semiconductor substrate and which isolates the photoelectric conversion section from an active region in which the pixel transistor section is disposed. The pixel transistor section includes a plurality of transistors. Among the plurality of transistors, in at least one transistor in which the gate width direction of its gate electrode is oriented toward the photoelectric conversion section, at least a photoelectric conversion section side portion of the gate electrode is disposed within and on the active region with a gate insulating film therebetween.

Abstract: A semiconductor device includes a solder bump overlying and electrically connected to a pad region, and a metal cap layer formed on at least a portion of the solder bump. The metal cap layer has a melting temperature greater than the melting temperature of the solder bump.

Abstract: The present invention provides a display panel and a display device, the display panel has an array substrate, and the array substrate has a substrate, a first inorganic film layer, at least one auxiliary cathode, a second inorganic film layer, and at least one via hole. The via hole is arranged in at least two voltage drop regions that are arranged sequentially. The via hole in each of the voltage drop regions is distributed evenly. A first voltage drop region is disposed opposite to a center or a side edge of the substrate.

Abstract: A non-volatile memory structure includes a substrate, a tunnel dielectric layer on the substrate, and several separate gate structures on the substrate. The gate structures are disposed within an array region of the substrate. Each gate structure includes a floating gate and a control gate on the floating gate. A first dielectric layer is formed above the substrate and covers the top surface of the tunnel dielectric layer. The first dielectric layer also covers the side surfaces and the top surface of each gate structure. Gaps between portions of the first dielectric layer on the side surfaces of two adjacent gate structures are fully filled with the air to form air gaps. Several insulating blocks are formed on the first dielectric layer, and they correspond to the gate structures. A second dielectric layer is formed on the insulating blocks and covers the insulating blocks and the air gaps.

Abstract: An integrated circuit device includes a first substrate, a second substrate, a first expanding pad, a second expanding pad and a bonding structure. The first substrate is provided with a first conductive portion, the second substrate is provided with a second conductive portion, the first expanding pad is formed on the first conductive portion to provide a first expanded contact area, the second expanding pad is formed on the second conductive portion to provide a second expanded contact area, and the bonding structure is formed between the first substrate and the second substrate, wherein the first expanding pad is bonded to the second expanding pad.