Abstract: A nonvolatile memory device having a field effect transistor for storing, which includes source and drain regions in a semiconductor substrate with a channel region interposed between them and a gate electrode above the channel region with a ferroelectric gate film sandwiched between them. Barrier metal is formed in contact with the source region of the field effect transistor for storing to make a Schottky diode in serial connection with the field effect transistor for storing. In reading information, voltage is applied to a serial circuit consisting of the field effect transistor for storing and the Schottky diode to turn the Schottky diode on.

Abstract: A nonvolatile memory device for storing data in a flip flop circuit comprising field effect transistors having respective ferroelectric gate films. A pair of writing/reading transistors is connected to the flip flop circuit. Each of the field effect transistors constituting the flip flop circuit retains its channel formation state because of a residual polarization in the ferroelectric gate film. Thus, when power goes OFF, the flip flop circuit retains its state just before power goes OFF. In this way, data can be stored on a nonvolatile basis, and stored data can be read without destroying the data. Additionally, no refreshing is needed, and therefore, a power demand in standby is reduced.

Abstract: An apparatus and method for improving the testability of six cell CMOS SRAM circuits. The technique involves adding transistors and the ability to effectively disable the precharge circuitry during the test mode. This makes the pull up transistors the only current source for switching the memory cell. An open or weak pull up transistor, which would appear as an intermittent soft failure under operational conditions because of the current sourcing of the precharge circuitry, becomes a hard stuck-at failure under the test conditions. Because the precharge circuitry is disabled for all memory cells, a slower memory clock speed is used for memory cycling during the test mode.

Abstract: An IC memory card system has a host for processing data, and an IC memory card removably connected to the host and incorporating a data recording medium implemented by an electrically erasable programmable semiconductor memory. The host comprises a system controller for sending to the memory card an address/data signal for distinguishing an address and data by a logical bilevel state, a read/write signal for distinguishing reading of data and writing of data in the semiconductor memory by a logical bilevel state, and an erase signal for erasing data stored in the semiconductor memory by a logical bilevel state as control signals, and bus clock pulses each being synchronous to a particular address and particular data.

Abstract: A semiconductor memory device comprises a plurality of word lines, a plurality of digit lines, a peripheral circuit area and a memory cell array area. The memory cell array area comprises a semiconductor substrate having a surface in which field oxide films are selectively formed, a plurality of operational memory cells arrayed on active regions within the memory cell array area, each of which includes a stacked capacitor and a switching transistor, and a plurality of dummy capacitors arranged within the memory cell array area at an adjacent portion to a boundary area between the memory cell array area and the peripheral circuit area. The dummy capacitor is to receive affections caused by an inferiority of the accuracy of patterning by a photolithography in replacement of the operational memory cells. The dummy capacitor is so formed over the field oxide film as to prevent said digit line at said boundary area to have a rapid slope or a large difference in level.

Abstract: A magnetic thin film memory device having information recorded in a magnetic thin film thereof by the direction of magnetization, and adapted to reproduce the recorded information on the basis of the voltage generated as a result of the change of the magnetization direction due to the extraordinary Hall effect, magnetoresistance effect or the like.A magnetic thin film memory device in which a magnetic thin film is formed of ferrimagnetic substance having perpendicular magnetic anisotropy, and producing extraordinary Hall effect in the composition of RE rich and having the minimum saturation field which enables recording in a small magnetic field and is hard to be influenced by temperatures.

Abstract: The described embodiments of the present invention provide a method in which the circuit configuration of redundancy circuitry in a random access memory can be simplified and the setting operation of the address of the defective memory cell is also simplified. In one described embodiment, the redundant circuit includes a fuse decoder (11), which functions as the address-generating circuit for the address of the defective memory cell, and a latch circuit (21). A write operation to the defective memory cell on the write port containing the fuse decoder (11) causes the address of the defective cell to be stored in the latch circuit. Each input/output port, except the input port using the fuse decoder, includes a comparator (22) for comparing the address for an operation on the respective port to the address stored in the latch circuit.

Abstract: A content addressable memory system has a plurality of associated circuit sets (12). Each circuit set has a tag memory element, a latching circuit and a data memory element. Each tag memory element stores a received tag in a first mode of operation and compares a received data tag to a stored data tag in a second mode of operation. In the second mode of operation, the tag memory element couples a first voltage supply terminal to an associated node in response to the comparison. Each latching circuit latches the voltage level present on its associated node during a first phase of a control signal. Each data memory element stores a data word and outputs the data word responsive to the latched voltage level of the associated latching circuit. The latching circuit continues to latch the voltage level and the data memory element continues to output its data word for an entire clock cycle.

Abstract: A semiconductor memory device is provided which includes a plurality of data lines, at least one redundant data line, one common data line, a plurality of column switches installed between the plurality of data lines and the redundant data line and one common data line, and a column decoder for controlling the plurality of column switches. The column decoder operates to turn the column switch on. The column switch is connected to a plurality of data lines, excluding any defective data and redundant data lines during the test mode state.

Abstract: A portable cosmetic mirror which includes a stand that may be adjusted to various heights for allowing a user to accurately position the mirror such that both hands may be utilized for cosmetic application, hairstyling, or the like. Alternate embodiments of the apparatus further include a hair dryer holding assembly for positioning a hair dryer for hands-free use with the mirror and a magnification assembly in which a magnifying lens is removably positioned upon the mirror.

Abstract: An optical memory which allows for the high-speed random access of two-dimensional information. Portions of a light receiver made from material with photovoltaic or photoconductive effect are connected to corresponding portions of a ferroelectric liquid crystal panel through an amplifier layer. To write, a light image is shown on the light receiver. When light striking each portion of the light receiver is sufficiently strong, the state of the corresponding part of the liquid crystal panel is changed. The state of the panel can be read with an image scanner for scanning the liquid crystal panel.

Abstract: A semiconductor memory device according this invention comprises a memory cell array in which cascade memory cells arranged in matrix form, each cell being composed of a plurality of MOS transistors cascade-connected to each other, and a plurality of information storing capacitors one end of each of which is connected to one end of each of the transistors, respectively, word lines equally connected to the memory cells in each row of the memory cell array, a bit line equally connected to each column of the memory cell array, a capacitor-plate line provided for each column of the memory cell array, and equally connected to the other end of each of the capacitor groups in the memory cells in the corresponding column, a bit-line precharger circuit connected to each of the bit lines, a capacitor-plate line precharger circuit connected to each of the capacitor-plate lines, and a sense amplifier circuit which is provided for column of the memory cell array, and which senses the potential between the bit line and the

Abstract: Non-volatile semiconductor memory integrated circuits which partition a main memory array into sub-arrays. Address lines of the main memory array are also partitioned into four groups. The first group and the second group are dedicated for the addressing of the sub-arrays. Each of the sub-arrays can be addressed by a simultaneous energization of a pair of address lines selected from the first and the second group. The third group and the fourth group are used for the addressing for individual memory cells in the sub-arrays. The simultaneous energization of a pair of address lines selected from the third and the fourth group can address any of the memory cells within a selected sub-array. The memory circuits of the present invention are applicable for memory cells with four terminals. In a first embodiment of the invention, the memory circuit is a one-bit wide circuit.

Abstract: An optical modulator in which waveguide regions are disposed at opposite ends of a modulation region to reduce the capacitance of the device and prevent pn junctions from exposure to air. On an n-side electrode there are laminated a substrate, an n-type clad layer and an optical modulation waveguide layer. A modulation region lies at the center of the optical modulation waveguide layer along the direction of travel of light, and two waveguide regions are disposed at opposite ends of the modulation region, respectively. On the optical modulation waveguide layer which constitutes the modulation region there are laminated a non-doped layer, a p-type clad layer and a p-side electrode, and a semi-insulating semiconductor is formed on the optical modulation waveguide layer which forms the two waveguide regions.

Abstract: A memory system with adaptable redundancy comprises address decoding means (200) for the selection of one of the rows R.sub.1 to R.sub.2 (n+1) in the memory array, according to the binary value of address A.sub.0, A.sub.1, . . . A.sub.nn incoming on bus 102. Block 200 comprises 2.sup.(n+1) blocks 201 being able to drive an activation signal on leads R.sub.1 to R.sub.2 (n+1), and having an output connected to a lead 206.Block 205 is able to drive an activation signal on lead RR according to signals present on leads 107 and 206, so as to select redundant row RR.sub.1 without the use of a redundant address decoder.

Abstract: A memory array of a static RAM or the like is divided in a word line extending direction to constitute a plurality of sub memory arrays SM0 to SM7, and array selecting signals for selecting the sub memory arrays and sub word line selecting signals for selecting sub word lines are combined to form word line selecting signals selectively. Main word lines M0000 to M0003 for transmitting those word line signals are arranged in parallel with the sub word lines SW000 to SW255. Sub word line drive circuits SWD000 to SWD255 are also coupled to the individual sub word lines for bringing the corresponding sub word lines selectively into selected states by combining at least 2 bits of the word line selecting signals.

Abstract: A voltage regulator is provided for controlling an on-chip voltage generator which produces a boost voltage across a charge reservoir for supply to one input of a plurality of word line drivers in a memory array. The regulator is configured such that the charge reservoir voltage will track the power supply voltage and the difference between the power supply voltage and the charge reservoir voltage will be maintained substantially constant over a predefined power supply range. The voltage regulator includes a bandgap reference generator, a first differential circuit for producing a transition voltage from the reference voltage and the power supply voltage, a first transistor for comparing the power supply voltage with the boost voltage, a second transistor for comparing the transition voltage with the reference voltage and a latching comparator for equating the signal outputs from the first and second transistors so as to define a control signal for the on-chip voltage generator.

Abstract: A flash EEPROM array (22) is erased and a threshold voltage distribution of the erased flash EEPROM cells (36, 39-46) is converged to within a predetermined voltage range by using a two-step erasing procedure. In the first step, flash EEPROM array (22) is electrically bulk erased using a conventional bulk erase procedure. Electrons are tunneled from the floating gate (38) to the source, causing cells (36, 39-46) to have a relatively low threshold voltage. In the second step, the threshold voltage distribution of the array (22) is converged to within the predetermined voltage range by grounding the source and drain of each cell (36, 39-46), while concurrently applying a high positive voltage to the control gate (27) of each cell (36, 39-46). Some electrons are tunneled back to the floating gate (38), thus converging the threshold voltage distribution to within a predetermined range.

Abstract: For directly observing from the outside the electrical characteristics of a memory cell, i.e., a voltage-current characteristic and threshold voltage in a non-volatile semiconductor memory device, there are provided same bit train selector means 5 for selecting and switching on a plurality of bit train selecting FETs(QB.sub.o, QB.sub.1. . . , QB.sub.n) each for interconnecting an external terminal 4 to which arbitrary voltage is applied and respective memory cell arrays 1a, 1b, . . . , 1n with each other and forming a current path extending from a specific memory cell FET (Q.sub.1) on the same bit train memory cell array to the external terminal, and a power supply circuit for supplying variable voltage to a gate of the specific memory cell FET (Q.sub.i). Hereby, there are improved the yield of articles and the accuracy of failure article analyses.

Abstract: In a method for data transfer between a plurality of memory cells and at least one input/output terminal of a semiconductor memory, and a semiconductor memory for carrying out the method, a memory cell address is defined by a control signal for a data transfer. A data transfer operation from or to the memory cells is controlled with an address control signal and an output enable control signal for defining a memory cell address with one of the two signals. A data transfer operation is subsequently initiated at a given logical linkage of the two control signals. An ensuing data transfer is controlled with the other of the two control signals.