Abstract: A semiconductor memory device comprises a memory cell array including a plurality of adjacently disposed first and second memory cell pairs, with bit lines defined in the memory cell array. Switching elements are interposed between the memory cells and the bit lines. Word lines are connected to the switching elements, for selecting one of the memory cells by operating the switching elements, so that data is written on and is read out from selected memory cell through the bit lines. Each bit line is arranged between the first and second memory cells, so that each bit line serves as a common bit line to the first and second memory cells. A buffer circuit is connected to each word line and the buffer circuit transmits the first, second and third select signals each having a different voltage level from each other. The switching elements are respectively connected to the first and second memory cells.

Abstract: Disclosed is a flash EEPROM cell needing only a 5 volt external source using an on-chip voltage multiplier circuit to provide high voltages necessary to effect Fowler-Nordheim tunneling during both the program and erase modes. Properties of dielectric layers between a floating gate and a control gate and between the floating gate and a drain region differ to facilitate programming and erasing of the floating gate. Also disclosed is a method for producing a flash EEPROM cell by forming the insulative layer between a floating gate and a control gate to have a capacitance lower than the capacitance of the insulating layer between the floating gate and a drain region.

Abstract: A projection lens system for a video projector for projecting a color image which is generated by combining red, green and blue images from an image source on a large screen. One lens element of a four lens optical lens system is disposed between an image-generating surface (or CRT) and an image combining unit for combining the images, and an oil chamber is provided by sealing the edges of the lens element and the image-generating surface. The flattening of the CRT's image-generating surface and a large aperture are attained by allowing the one lens to correct field curvature aberration and the other lenses to correct coma aberration. Separate cooling for respective CRTs enhances cooling devices efficiency and facilitates CRT movement adjustment for correcting chromatic aberration.

Abstract: A dynamic random access memory device is equipped with an internal power supply system for selectively distributing a step-down power voltage to internal component circuits, and the internal power supply system comprises a feedback loop for regulating the step-down power voltage on an internal power supply line to a reference voltage, a voltage detecting circuit monitoring an internal power voltage line to see whether or not the step-down power voltage is decayed to a critical level for producing a gate control signal, and an auxiliary variable load transistor coupled between the external power supply line and the internal power supply line and responsive to the gate control signal for supplementing current to the internal power supply line, wherein the critical level is inversely proportional to the external power voltage while the external power voltage is higher than the reference voltage, thereby preventing the step-down power voltage from undesirable overshoot upon production of the gate control signal.

Abstract: A refresh mode switching signal generating circuit generates a refresh mode switching signal of an H level or an L level depending on whether a particular bonding pad is wire-bonded to a power supply terminal of a package. In response to the refresh mode switching signal, the refresh mode switching circuit switches a cycle number in a refresh mode of a semiconductor memory device, so that the cycle number in a refresh mode can be changed according to requirements of users.

Abstract: In case an address is to access a defective memory cell, a defective memory cell in a memory cell area contained in one of paired memory mats is selected in parallel with a redundant memory cell in a redundant memory cell area contained in the other memory mat. At this time of selecting the redundant main word line for selecting the redundant memory cell, there is not required the logical operation for deciding whether or not the redundant use of the access address fed from the outside is proper. For example, the redundant main word line is set to the select level on the basis of a chip select signal. As a result, the drive start timing of the redundant main word line is not delayed in the least from the drive start timing of the main word line. Thus, it is possible to prevent the event that the select drive timing of the redundant sub word line is delayed on account of the delay in the drive timing of the redundant main word line.

Abstract: The present invention provides a memory device for preventing data circulating on a plural number of linear CCD array from being corrupted, for accessing data at a high speed, and for reducing the device's electric power consumption.A memory device according to this invention downsizes a block of a memory cell by circulating data on a plural number of linear CCD arrays which are for storing data by an electric charge on a cell and keeping analog data, which sets a clock generation means for circulating data on all arrays and another clock generation means for circulating at a high speed only the array loops having necessary data.

Abstract: A reset mechanism for a random access memory array comprises an auxiliary reset circuit, which does not require modification of the contents of the memory itself. For a random access memory capable of storing M, N-bit words, the auxiliary mechanism includes a plurality of M reset state circuits that are respectively associated with the M words of memory. The reset state circuit preferably comprises an additional `resetable` memory cell for each word of memory, which is integrated within the structure of the memory itself. In order to reset one or more words of memory, the associated reset state circuits are placed in a reset state-representative condition. The state of each reset state circuit is used to controllably mask (e.g. is logically ANDed with) the contents of its associated word of memory, whenever that word is read out. If the reset memory cell has been cleared, then regardless of the contents of its associated word in memory, the mask will cause the addressed memory word to be output as all zeros.

Abstract: A polygon mirror is made up of a rotor including a ceramic ring, a yoke and a mirror surface formation member. The yoke and the mirror surface formation member are secured to an outer periphery of the ceramic ring. A radial dynamic pressure bearing is defined by an inner periphery of the ceramic ring and an outer periphery of the fixing shaft. A thrust dynamic pressure bearing is defined by both end surfaces of the ceramic ring and surfaces of a thrust plate fixedly secured to the stator and confronting both end surfaces of the ceramic ring. The ceramic ring, the yoke and the mirror surface formation member are integrated by the material making up the mirror surface formation member during the molding of the member to form the rotor.

Abstract: A nonvolatile random access memory (60) includes a ferroelectric memory array (62). The memory array (62) includes memory cells (86-89 and 91-96) arranged in intersecting rows and columns, where the memory cells (86-89 and 91-96) are coupled to bit lines and word lines. Drive lines are disposed parallel to the bit lines and drive line segments are disposed parallel to the word lines. A drive line segment is coupled to a predetermined number of the memory cells of a row. Coupling transistors (80, 82, 84, and 90) couple a drive line segment to a drive line in response to the word line being selected. The ferroelectric memory array (60) provides the advantage of eliminating a change in the polarization state of non-accessed memory cells connected to a selected drive line, and also provides the advantage of reduced energy consumption.

Abstract: A high-speed memory employing the pipeline technique is disclosed, in which the minimum operating cycle time is reduced by use of a latch circuit for a small signal using a bipolar transistor. A small-signal latch circuit operating at a signal smaller than an output signal level is inserted between an amplifier circuit for amplifying the data held in a memory cell circuit and an output buffer circuit. A switch signal is also interposed between the latch circuit and the amplifier circuit, thereby shortening the cycle time.

Abstract: Binoculars designed to provide a large aided static field of view are provided. The binoculars are characterized by S/D ratios of above 2.8, where S is the binoculars' aided static field of view calculated by multiplying the binoculars' magnifying power by the binoculars' semi field of view in object space and D is given by tan.sup.-1 [(R.sub.ex +1.5)/13], where R.sub.ex is the radius of the binoculars' exit pupil and where R.sub.ex and the constants 1.5 and 13 are measured in millimeters. As a result of the increased S/D ratio, the binoculars of the invention minimize the sensation of tunnel vision which normally occurs when binoculars are used and reduce the user's apprehension of missing activities in his or her peripheral vision. In certain embodiments, a movable field lens unit is employed to provide variable power and a negative corrector lens unit is employed for aberration correction and to minimize the size of the binoculars. The binoculars are suitable for mass production and general consumer use.

Abstract: The multi-dimensional optical memory utilizes the wavelength and intensity dimensions to effect a high density record. With incorporation of a broadband light source, scanning monochromator and photo detector array, a high speed random access optical memory system is realized. The system is executed in terms of a silicon based manufacturing technology allowing advantages of low cost and small physical size resulting from photolithographic batch-processing producibility.

Abstract: A semiconductor memory device of FIFO type is disclosed. The memory device has a test function for easy analysis of irregularities. A read data register for holding read data from the memory cells and a write data register for holding write data to the cells are provided corresponding to the memory cell array of the memory device. Further, bypass switch means for directly transferring data from the write data register into the read data register is provided.

Abstract: A present invention provides a semiconductor memory device including a capacitor, in which the capacitor comprises an upper electrode, a lower electrode, a ferroelectric capacitor insulating film disposed between the upper electrode and the lower electrode, and a side wall spacer consisting of an insulating material being formed on the side wall of the lower electrode and/or the ferroelectric capacitor insulating film.

Abstract: A stacked delta cell (SDC) capacitor using a modified stacked capacitor storage cell fabrication process. The SDC is made up of polysilicon structure, having an inverted deltoid cross section, located at a buried contact and extending to an adjacent storage node overlaid by polysilicon with a dielectric sandwiched in between. The addition of the polysilicon structure increases storage capability 120% without enlarging the surface area defined for a normal stacked capacitor cell.

Abstract: A semiconductor memory device facilitated with a test circuit having a simple construction of a plurality of MOSFETs having their individual gates connected with a plurality of word lines in a memory array; and a testing pad for detecting the presence of an electric current flowing between the sources and drains of the plurality of MOSFETs. If the word line is short-circuited to the power supply to achieve an intermediate potential equal to or higher than the threshold voltage of the MOSFETs, an electric current will flow through the MOSFETs so that the presence of the short-circuit between the word lines and the power supply can be accurately detected.

Abstract: A shared sense amplifier circuit incorporated in a dynamic random access memory device is coupled at input/output nodes with dummy cells implemented by n-channel enhancement type field effect transistors for pulling one of the input/output nodes down upon access to one of the memory cells, and one of the enhancement type dummy cells rapidly turns off so that undershoot takes place at the associated input/output node due to channel resistance between the shared sense amplifier circuit and a bit line pair, thereby enlarging differential voltage applied between the input/output nodes of the shared sense amplifier circuit.

Abstract: Power consumption of a serial EEPROM is reduced while simultaneously precluding data corruption during write operations. These results are achieved by operating a brownout detector in the device to sense EEPROM supply voltage below a predetermined level and thereupon to place the EEPROM in a reduced power mode, but only during an interval that a write sequence is taking place. Such an interval includes loading of data in a temporary storage cache and writing the loaded data into the EEPROM. At the same time that the low voltage level is detected during a write sequence, any load or write operation then in progress is aborted. The brownout detector is intentionally left disabled or in a sleep mode during any read mode or standby mode since there is no jeopardy of corrupting the EEPROM memory during those times.

Abstract: In response to a plurality of address signal input from the outside in sequence, an erase information inputting section controls an erase information holding section corresponding to the batch erase block to be erased so as to hold an erase information data. By repeating this operation in sequence, the erase information data are stored in the erase information holding sections corresponding to the plural batch erase blocks to be erased. Successively, on the basis of the erase information data stored in the erase information holding sections, block erasing sections are activated to erase all the nonvolatile memory cells of each of the corresponding blocks where the erase information data are held.