Abstract: The circuit and method of this invention provide for rapid and reliable detection of depleted or nearly-depleted cells in a column. The circuit is formed on the substrate of a nonvolatile, integrated-circuit memory including rows and columns of memory cells. The drain of each memory cell is connected to a drain-column line and the control gate that is connected to a wordline. One input of a sense amplifier is connected to the drain-column line. The other input of the sense amplifier is connected to a current reference formed on said substrate. The wordline is connected to a wordline test voltage and the output of the sense amplifier is coupled to an output pin of the integrated circuit. The current through the drain-column line is compared with the current through the current reference and, if the current through the drain-column line is sufficiently close to the current through said current reference, a signal is transmitted to an output pin of the integrated circuit.

Abstract: An ignitor (118) comprises a body portion (120) connected with an electrical supply cable (122) and an electrode portion (124) removably mounted within the body portion (120). The body portion (120) includes a capacitor defined by an outer, electrically conductive shell (126) of the body portion, and an inner, tubular capacitor plate (134). The inner, tubular capacitor plate (134) is held within the body portion (120) by means of a connector assembly (132) which is held in place by a dielectric potting compound (136).

Abstract: An associative memory device has associative memory cells arranged in matrix and each implemented by a parallel combination of two electrically erasable and programmable non-volatile memory transistors, and a multi-bit data code stored in a row of associative memory cells allows the two electrically erasable and programmable non-volatile memory transistors of each associative memory cell to selectively enter the programmed state so that a multi-bit key code is checked to see whether or not drain current flows through the electrically erasable and programmable non-volatile memory transistors into a source line.

Abstract: The semiconductor device includes a voltage generator for generating selectively a signal of a first level or a second level onto a first supply line, and a voltage converter using voltage signals on the first supply line and a second supply line for producing a signal of the voltage level on the first or the second supply line in accordance with an input signal, and a voltage level shifter for detecting the level of the voltage on the first supply line to shift in voltage level a signal on the second power supply line toward the first level when the voltage on the first supply line approaches the first level. The difference of the voltages on the first and second supply lines can be reduced to improve the break-down characteristics of a transistor included in the voltage converter, resulting in a reliable semiconductor device.

Abstract: Various optimizing techniques are used for erasing semiconductor electrically erasable programmable read only memories (EEPROM), An erase algorithm accomplishes erasing of a group of memory cells by application of incremental erase pulses, Techniques include a 2-phase verification process interleaving between pulse applications; special handling of a sample of cells within each erasable unit group; defects handling; adaptive initial erasing voltages; and single- and hybrid-phase algorithms with sector to sector estimation of erase characteristics by table lookup. Techniques are also employed for controlling the uniformity of program/erase cycling of cells in each erasable unit group, Defects handling includes an adaptive data encoding scheme.

Abstract: A detecting amplifier has a first transistor arranged between a first positive power source and a semiconductor memory and connected in series to the first positive power source and having a low turning-on resistance value; a second transistor arranged between the first transistor and the semiconductor memory and connected in series to the first transistor and connected to a negative feedback circuit having an inverting element; and a third transistor arranged between a second positive power source and an output section of the detecting amplifier and connected in series to the second positive power source and constituting a current mirror structure together with the first transistor. In accordance with this detecting amplifier, an access time to a memory transistor is maintained in a short state and a detecting operation of the detecting amplifier is reliably performed.

Abstract: A memory in which a portion of a digit line is isolated from the remainder of the digit line during a write cycle has improved performance. In the conventional architecture of a memory device, cells are arranged in rows and columns and a sense amplifier is employed for a pair of columns, located between a pair of complementary digit lines. An embodiment of the present invention in this architecture provides improved means for isolating the sense amplifier during a write cycle.

Abstract: A flash memory device having a plurality of flash array blocks and a block status register circuit containing a block status register for storing a block status for each flash array block. A flash array controller circuit in the flash memory device performs program or erase operations on the flash array blocks, and maintains the block status in each block status register. An interface circuit in the flash memory device enables read access of the block status registers over a bus.

Abstract: An improved circuit is provided for extending the write-recovery time of a high speed memory into the next memory access cycle. In the preferred embodiment, the address buffer circuits turn off at a suitable high rate for read but are controlled to turn off more slowly for a write and to thereby extend the write select signal. In a specific address buffer circuit, FETs are supplied a reduced drain-source current during write and thereby are made to switch at a suitably slower speed.

Abstract: An apparatus for relieving the standby current fail of a memory device which completely relieves a memory device by suppressing the increasing standby current consumption when the standby current is failed by stress during or after fabricating process without any change of standby conditions in a memory device having NAND-type cell array structure, and by using the other data correcting way. By connecting the transistors for the ground string selecting operation in series to the string transistors in order to selectively form the electrical path between the transistor connected to the word line and the ground node, even though the breakdown of the NAND cell occurs, the standby current fail can be prevented by selectively turning on or off the current path in response to the address decoding signal.

Abstract: A plurality of data line pairs incorporated in a dynamic random access memory device extend over circuit components in parallel to a bit line pairs, and propagate a data bit between a read/write amplifier circuit and a sense amplifier unit shared between two memory cell blocks, wherein a column selector selectively charges one of the plurality of data line pairs before propagating the data bit so that a concentrated column selecting system and the data line pairs over the circuit components make the random access memory device possible to be fabricated on a relatively small semiconductor chip.

Abstract: In a random access memory comprising pairs of input/output bus lines (7.sub.0 to 7.sub.3) transferring write data to the memory cells (3a) and read data from the memory cells, input/output terminals (10.sub.0 to 10.sub.3) corresponding to the pairs of input/output bus lines, and input/output buffer circuits (9.sub.0 to 9.sub.3) respectively corresponding to the input/output terminals and also corresponding to said input/output terminals, an access control signal is applied to the input/output terminal (10.sub.0) in a period in which the input/output terminal is not used for input or output of write data or read data, and transfer of read data through each of the input/output buffer circuits is permitted or inhibited on the basis of the access control signal.

Abstract: In an imaging apparatus, provided is an optical device which is capable of changing the magnifying power thereof. The optical device includes a zoom lens system having a power varying lens group and a correction lens group both of which are movable in the direction of the optical axis of the zoom lens system with respect to the zoom lens system. The zoom lens system is moved in the direction of the optical axis of the zoom lens system, and the power varying lens is driven synchronously with the movement of the zoom lens system. Further, the zoom lens system and the correction lens are moved in accordance with a magnifying power and data representing the amount of the displacement of the zoom lens system respective to the optical axis and the displacement of the correction lens with respect to the optical system.

Abstract: A dynamic type semiconductor memory device includes a pair of transistors provided in a signal line for transmitting a sense amplifier drive signal to sense amplifiers. The transistors of the pair are provided in parallel with each other, and are activated to couple the sense amplifiers to a source of generating the sense amplifier drive signal. One of the pair of transistors is made nonconductive in a refresh mode of operation. This arrangement reduces the peak value of a current for charging and/or discharging bit lines by the sense amplifiers in the refresh mode of operation, and reduces a noise on a power source line or a ground line at an on-board level, resulting in stable operation of a system.

Abstract: A MOS memory device operating at high speed which is so constructed as to hold the sense amplifier activating signals SAP and SAN at high potential and at low potential, respectively, even after the completion of a memory access, and keep the sense amplifier 30a in activated state to hold read data from memory cells. This memory device includes a block decoder which designates mutually different cell array blocks synchronized with a row selection signal RAS and a column selection signal CAS so that it is possible at the time of input of the column selection signal CAS to execute write/read operation in page mode that extends over the cell array blocks.

Abstract: In a memory cell array having a plurality of memory cells connected to store physical information levels different in adjoining pairs of complementary data lines, those pairs of the memory cells, with which are connected the memory cells for storing the physical information levels in an identical pattern, are connected with a plurality of input/output lines by a column select circuit, so that the plurality of memory cells may be caused to perform the writing operations simultaneously in a test mode by feeding an identical write signal to the plurality of input/output lines. In the test mode, moreover, the input write data are processed so that the physical information levels of adjoining memory cells to be simultaneously written in the plurality of memory cells may be coincident.Since the information levels of the adjoining bits can be made physically identical or different by combining the address selection and the write data, it is possible to shorten the testing time.

Abstract: A DRAM comprising a memory cell array having a dynamic type memory cell having one MOS transistor for transfer gate and one capacitor for data storage with one end connected to the transistor, a word line connected in common to the gate of each transistor in each row of the memory cell array, a bit line connected in common to each transistor in each column of the memory cell array, a bit line precharge circuit provided so as to precharge the bit line of the memory cell array at a predetermined timing, a capacitor common line provided so as to correspond to a pair of complementary bit lines of the memory cell array and connected in common to the other end of the capacitor of the memory cell, a capacitor common precharge circuit provided so as to precharge the capacitor common line at predetermined timing, capacitor common line transfer gates for connecting the capacitor common line to the input nodes of a sense amplifier and on/off controlled at a predetermined timing, and bit line transfer gates for connectin

Abstract: A DRAM having bidirectional global bit lines is defined such that local bit lines connected to corresponding memory cells and separative global bit lines connected to the local bit lines are commonly connected to local bit lines so as to read data stored in the cells or write data to the cells in a bidirectional data access manner. According to the DRAM of the present invention, the sense amplifiers, input and output lines and switching elements for column decoding, which generally are located between adjacent cell arrays, can be advantageously positioned without decreasing the characteristics of the DRAM element. In addition, the DRAM of the present invention employs an open bit line structure rather than a folded bit line structure, thereby improving a packing effect as well as a S/N (signal-to-noise) characteristic, remarkably.

Abstract: In a highly integrated semiconductor memory device, apparatus for setting a stress mode without applying a stress voltage from the exterior is provided. A triggered time point T.sub.S to a stress mode can be set by greatly raising an internal supply voltage when the external supply voltage is raised to a voltage over the stress voltage.

Abstract: An erasable programmable memory device has a number of data storage blocks. Each block has an endurance characteristic that at least roughly defines the number of times data may be erased from and written to the block before it wears out in that data cannot then be further erased from and written to the block. A redundant data storage block of memory capacity and endurance similar to that of each of the other data storage blocks is disposed in parallel with a selected one of the latter for which higher endurance is desired. This enables identical data to be written simultaneously to the two blocks and thus considerably increases the endurance of the selected block by virtue of the fact that identical memory cells in both blocks must fail before the endurance of the selected block will be depleted. After the selected block has been designated for high endurance and placed in parallel with the redundant block, a fuse may be set to prevent alteration of that designation.