Abstract: In a serial memory, data signal holding circuits for temporarily holding data read from memory cells are provided as a data register. One holding circuit includes a latch circuit and capacitors connected to input/output nodes of the latch circuit, respectively. The capacitors contribute to stabilizing the latch function by the latch circuit. Therefore, when transistors turn on in response to a serial selection signal at a high level, the latch circuit is prevented from being inverted by the potentials of a serial bus line pair. Accordingly, generation of reading errors is prevented.

Abstract: A method for producing electrically erasable and programmable read-only memory cells with a single polysilicon level, including the use of a sacrificial layer of silicon oxide to produce a high-thickness silicon oxide layer on the active area. The active area of the cell is protected from heavy source and drain implantation in order to improve reliability.

Abstract: A semiconductor memory, such as a static random access memory (SRAM), utilizes short data buses to improve operation speed. The semiconductor memory includes a first group of output ports for receiving data through a first set of bit line pairs, a first data fetching gate and a first data bus for the first set of bit line pairs, disposed along a first long side, a second group of output ports for receiving data through a second set of bit line pairs, and a second data fetching gate and a second data bus for the second set of bit line pairs, disposed along a second long side.

Abstract: An output buffer circuit is disclosed that operates in low voltage applications but can be programmed using standard programmers at high voltage. The output buffer circuit provides for detecting a program verify logic signal from the programmer and slowing the output driver transistors when that signal is detected. In so doing, the noise problems associated with the higher voltages of programming a EPROM device are eliminated while at the same time allowing the output buffer circuit to operate at the required performance levels during normal operation.

Abstract: A device for providing multiple optical ports on an optical gunsight with a minimum impact on eye relief and which preserves full viewing angle is provided. A housing which includes first and second hinged housing portions is clamped about the circumference of the gunsight. A lens assembly is supported by one of the housing portions having an optical axis in line with the gunsight optical axis. A front lens and aspheric optical distortion lens relay a gunsight image to the beamsplitter. The beamsplitter directs first and second images from a gunsight image along axes which are in line an perpendicular to the gunsight axes. The assembly also includes identical third and fourth lenses which produce images of the gunsight exit pupil along each of these axes.

Abstract: A semiconductor memory device according to the present invention includes a memory cell array, internal circuits for reading and writing of data of the memory cell array, a test mode controller, and power-on-reset circuits. The test mode controller sets a test mode of the memory cell array in response to a predetermined pattern of change of logic levels of at least several control signals out of a plurality of control signals for controlling the internal circuits. The power-on-reset circuits set the test mode controller in an initial state over a variable period which is defined based on a timing of change of a logic level of a control signal determining a timing of setting of the test mode out of the at least several control signals, in response to power-on. As a result, it is possible to prevent the semiconductor memory device from erroneously entering the test mode caused by a noise or the like after power-on.

Abstract: Each of memory cells of a semiconductor memory device comprises a transistor connected between a node and a node, a transistor connected between the node and a node, a transistor connected between a node and a node, and a transistor connected between node and a node. Each of the nodes is connected to either of a first potential line and a second supply line in a program unit when it is manufactured, and each of the nodes is connected to either of the first and the second ground lines in a program unit when it is manufactured.A supply potential is supplied to the first supply line, and the supply potential or the ground potential is selectively supplied to the second supply line. The ground potential is supplied to the first ground line, and the ground potential or the supply potential is selectively supplied to the second ground line.

Abstract: A method and apparatus for flash EEPROM refresh is provided in which the control gate of a particular memory cell is read at an elevated control gate voltage (42). It is next determined whether the cell has been programmed (44). If the cell has been programmed, then the next memory cell is read (46). If it is initially determined that the cell has not been programmed (44), then the particular memory cell is read at a lowered control gate voltage (48). It is then finally determined whether the cell has been programmed (50). If it is determined that the cell has not been programmed, then the next cell is read (46). If it is determined that the cell has been programmed (50), then the memory is refreshed (52). After refresh, the next memory cell is read (46).

Abstract: A differential latching inverter uses a pair of cross-coupled inverters having a skewed voltage transfer function to rapidly sense a differential signal on a pair of bit lines in a random access memory and provide high speed sensing during a read operation. The differential latching inverter may also include a pair of symmetrical transfer function output inverters and additional pull-up circuits to enhance high speed operation. The differential latching inverter may be used in a memory architecture having primary bit lines and signal bit lines, with a differential latching inverter being connected to each pair of signal bit lines. The primary bit lines and signal bit lines are coupled to one another during read and write operations and decoupled from one another otherwise. The read and write operations may De internally timed without the need for external clock pulses in response to a high speed address change detection system, and internal timing signals generated by delay ring segment buffers.

Abstract: An improved architecture for an array of flash EEPROM cells with paged erase is provided. The array is formed of a plurality of half-sectors. In each sector, the sources of the memory cell transistors are connected to a separate individual ground line. A ground line circuit is provided for generating a half-sector ground line signal. The separate individual ground line is connected to the ground line circuit for receiving the half-sector ground line signal which is at a predetermined positive potential during erase.

Abstract: A high-resolution synthetic aperture telescope system includes a primary mirror which is a section of the aperture to be synthesized; and a device for rotating the primary mirror section through a number of angular positions about the aperture being synthesized to obtain a plurality of component images of an object, at least one from each of the positions.

Abstract: A three-port Josephson memory cell has one input port (a data line) and two output ports (first and second sense lines). The memory cell receives a write enable pulse on a write line to store a bit of data from the data line as circulating supercurrent. The memory cell also receives a first read enable pulse on a first read line to enable assertion of the stored data onto the first sense line, and receives a second read enable pulse on a second read line to enable assertion of the stored data onto the second sense line.

Abstract: A dual port video random access memory device operates as a dual port by adding a serial access memory portion to a dynamic random access memory portion. A block write function can be selectively performed by multiplexing either a decoded signal corresponding to the two least significant bits of a column address or a 4 bit data input. An improved memory device construction is taught which reduces the total number of transistors necessary to perform the dual port function of prior art memory devices. As a result, chip layout and chip miniaturization can be realized.

Abstract: A DRAM furnishes power management circuits that remove power from circuits on the DRAM that are not necessary for self-refresh and that turn on and off other circuits necessary for self-refresh in timed relation to the refresh cycle. The power management circuits include a counter and simple decoder circuits that decode the binary output of the counter.

Abstract: A vertically integrated DRAM cell having a storage time of at least 4.5 hours at room temperature, formed from a wide-bandgap semiconductor such as GaAs or AlGaAs, in which an n-p-n bipolar access transistor is merged with a p-n-p storage capacitor, with the middle p-n layers being common to both. Similarly, a p-n-p transistor can be merged with an n-p-n storage capacitor.

Abstract: An electrochromic system for controlling the color state of an electrochromic pane. The charge needed to obtain the desired color is determined from the discharge potential of the system and the coloration set-point. An integrator measures the charge passing through the system and compares it to the charge to be transferred. This charge is measured by a differential amplifier which compares a discharge potential measured by a capacitor with a selected color set-point.

Abstract: A method and system for creating a three dimensional viewing illusion in true color uses left and right images of a stereo pair which are designed to be viewed respectively by the left and right eyes of a viewer as a single three dimensional image. In synchrony therewith, light from a light source device is alternately shown to the right and left eyes of the viewer so that while the eyes do view both of the left and right stereo images, the contrast of the eye receiving both the light and the stereo image designed for the other eye is reduced. In the various embodiments, the light source device includes a left and a right light source. In one embodiment the light sources are collimated and suitably aimed at the respective eyes. Preferably, the position of the eyes are also tracked and the aiming of the sources is adjusted as the viewer moves. In another embodiment, the light sources are mounted adjacent the associated eye of the viewer on an object which is worn by the viewer.

Abstract: In a semiconductor memory device including memory cells connected to word lines, one of the word lines is selected by a word line selecting circuit. A word line driving circuit receives an activation signal and a pseudo-acceleration signal to generate a driving signal for driving the selecting circuit. The driving signal is generated by delaying the activation signal with a definite delay time period which is changed in response to the pseudo-acceleration test signal, to thus perform a pseudo-acceleration test upon the word line driving circuit.

Abstract: A data reading circuit of the present invention comprises a pair of data buses supplied with complementary potentials respectively, a first reference voltage source having a first potential, a second reference voltage source having a second potential, a first switch connected to the first reference voltage source and the pair of data buses and responsive to a first clamping signal thereby to electrically connect the first reference voltage source to the pair of data buses, and a second switch connected to the second reference voltage source and the pair of data buses and responsive to a second clamping signal thereby to electrically connect the second reference voltage source to the pair of data buses.

Abstract: An integrated circuit memory array has a data input/output, a Read/Write* signal input, a row decoder, and a column decoder. An input circuit inputs a beginning and ending address to an on-chip memory controller which then sequentially addresses the beginning address, all the cells between the beginning address and the ending address, and the ending address, causing the array to sequentially output or input data from the sequence of cells, depending on the state of the Read/Write* signal.