Abstract: This disclosure relates to an electrically alterable memory device which can be switched from a high resistance state to a low resistance state. The device increases the concentration of electrically active impurities at correspondent electrode to which respective impurities would migrate during a large number of set-reset cycles. This lessens the decline in the threshold voltage caused by the electromigration of those impurities. The device includes a layered structure in which a layer rich in electrically active impurities is placed between memory material layer and its respective electrode and another layer. A fitted thin layer of dielectric is placed between a memory material layer and the other electrode. The memory layer includes an interface of chalcogenide films. A tellurium layer with a concentration of electrically active impurity 2.5%-4.

Abstract: A column latch and a high voltage switch connected to each bit line are eliminated, and an address counter and the data latch are newly provided. The data latch is arranged between an I/O buffer and a Y gate. In a programming cycle, the address counter is activated and transfer gates in the Y gate are successively selected. Consequently, a high voltage Vpp or 0 V is applied periodically to bit lines in the memory cell array in accordance with the write data stored in the data latch.

Abstract: A power supply system incorporated in a dynamic random access memory device distributes a step-down power voltage and a boosted voltage to a sense amplifier unit and a word line driver for allowing switching transistors of the memory cells to transfer the step-down voltage level to the storage capacitor without any voltage drop in read-out and write-in modes, and the switching transistors and the storage capacitors are subjected to inspections through a burn-in testing process before delivery from the manufacturing factory so as to actualize potential failure; however, either switching transistors or storage capacitors are insufficiently stressed in the burn-in testing process, and the power supply system changes the ratio of the boosted voltage to the step-down power voltage between the read-out and write-in modes and the burn-in testing process so that the switching transistors and the storage capacitors are sufficiently stressed.

Abstract: An asymmetric static random access memory cell (50 and 53) includes polysilicon load elements (55 and 56), N-channel pull-down transistors (57 and 58), and N-channel coupling transistors (59 and 60). One of the coupling transistors (59 and 81) has a channel width that is less than the channel width of the other coupling transistor (60 and 80). The asymmetric cells (50 and 53) are located close to power supply voltage terminal V.sub.SS, while conventional symmetrical cells (51 and 52) are located apart from the power supply voltage terminal V.sub.SS. The asymmetric cells (50 and 53) correct an imbalance in the ground path caused by a parasitic resistance (83 and 86) of a diffusion layer (94) that is used to couple the asymmetric cells (50 and 53) to ground potential. The asymmetric cell (50 and 53) improves cell stability without degrading performance or increasing cell area.

Abstract: An optical switching device for switching arbitrarily polarized optical signal beams includes a plurality of polarization-independent switching cells arranged in matrix form. Each polarization-independent switching cell is independently controllable to selectively direct received optical beams along at least a selected one of two axes. The device can be three-dimensionally expanded to increase the number of output ports to which the optical beams can be selectively switched, in which case the matrices can share integrally constructed polarization-independent switching cells.

Abstract: A semiconductor memory whose sense amplifier having a bias circuit and a charging circuit is provided. The bias circuit includes a first MOSFET whose source is connected to a digit line, a second MOSFET provided between a power source and the first MOSFET and becoming a load of the first MOSFET, and a first inverter whose input terminal and output terminal are connected respectively to the source and gate of the first MOSFET. The charging circuit includes a third MOSFET whose source is connected to the source of the first MOSFET, a second inverter whose input terminal and output terminal are connected respectively to the source and gate of the third MOSFET, and a fourth MOSFET provided between the drain of the third MOSFET and the power source and receiving through the gate thereof an output signal of an address transition detector which detects an address change and generates a pulse signal.

Abstract: A bipolar transistor Q.sub.1 having a collector formed of a substrate region SUB of a MOS transistor M.sub.1, a base formed of the drain region of the MOS transistor and an emitter formed on the base and connected to a bit line BL is connected between the bit line BL and a memory cell MC formed of the MOS transistor M.sub.1 and and a capacitor C.sub.1 and the current amplifying operation of a bipolar transistor is used for data readout.

Abstract: A main portion of a first word line extends in a direction connecting one diffusion region to the other diffusion region of an access transistor and is located between memory cells, and diverging portions of the first word line alternately extend from both sides of the main portion of the first word line to corresponding adjacent memory cells. A bit line extends in a direction perpendicular to the direction connecting one diffusion region to the other diffusion region, and a second word line extends along the diverging portion of the first word line. When stored data is to be read out from a memory cell, a positive voltage is applied to one first word line corresponding to the memory cell whose data is to be read out, and a zero voltage is applied to the remaining first word lines.

Abstract: A semiconductor memory device comprises a plurality of memory cells arrayed in matrix and each connected to a word line and a pair of bit lines for supplying a power supply voltage. A bit line load is connected to the pair of bit lines to control a current flowing through a memory cell by the power supply voltage. The semiconductor memory device also comprises a control circuit, connected to the bit line load, for detecting a variation in the power supply voltage, outputting a control signal corresponding to a value of the power supply voltage the variation of which is detected, and controlling activation/inactivation of the bit line load by changing a resistance thereof.

Abstract: An erasable programmable memory device has a number of contiguous data storage cells forming the data memory of the device. The address of one of these data storage cells is stored to designate it as a cell which is to be write protected so that its contents may not thereafter be erased or overwritten. Information is also stored to identify the total number of contiguous data storage cells to be similarly write protected commencing with the cell whose address is stored to designate write protection. The contents of the designated and identified cells are then made permanent. Write protection of the designated and identified cells is accomplished by comparing each write operation address with the addresses of the data storage cells encompassed within the protected area, and if it is within that area, aborting the write operation.

Abstract: A semiconductor memory device has plural memory cell blocks, each including memory cells storing data therein. A data bus and switching circuits transfer data from the memory cells to the data bus in response to a first logic level signal applied thereto. Column lines each have first and second ends. Each column line is connected to the corresponding switching circuit in each of the memory cell blocks. A column decoder, coupled to the first end of the column lines, provides the first logic level signal to one of the column lines upon the memory cell blocks being accessed. Potential setting circuits are coupled to the second end of the column lines, and preliminarily set the respective column lines to be in a predetermined potential so that each switching circuit is inactive prior to the column decoder providing the first logic level signal. All the memory cells in an array can be prevented from becoming inoperative even if a column line is broken.

Abstract: A zoom lens of the rear focus type is disclosed, including, from front to rear, a first lens unit of positive refractive power, a second lens unit of negative refractive power, a third lens unit of positive refractive power and a fourth lens unit of positive refractive power, the second lens unit being moved toward the image side when zooming from the wide-angle end to the telephoto end, while moving the fourth lens unit to compensate for the image shift with zooming, and focusing being performed by moving the fourth lens unit. The third lens unit consists of a positive single lens having an aspheric surface. The fourth lens unit includes a negative first lens and a positive second lens, and at least one of lens surfaces of the the first and second lenses is aspherical.

Abstract: A nonvolatile memory is described that includes a memory array and control circuitry coupled to the memory array for controlling memory operations with respect to the memory array. The control circuitry can operate at a first power supply voltage and a second power supply voltage. A configuration circuit is coupled to receive a power supply voltage indication signal for selectively configuring the control circuitry in accordance with the power supply indication signal to operate at one of the first and second power supply voltages. When the power supply voltage indication signal is in a first state, the configuration circuit configures the control circuitry to operate at the first power supply voltage. When the power supply voltage indication signal is in a second state, the configuration circuit configures the control circuitry to operate at the second power supply voltage.

Abstract: An optical system (10) includes a three mirror anastigmat telescope (12) and imager optics (14). The imager optics (14) provide narrow and wide field of view staring of the viewed scene. The optical system is positioned in a turret assembly (50) and folded to provide a sensor. The sensor includes an output laser beam generator (90). The telescope (12) is shared by the infrared system and the laser (90) to provide a simplistic and compact turret arrangement (50) which is well suited for aircraft targeting and designation purposes.

Abstract: Devices for deflecting an optical beam under the action of an ultrasonic beam propagating in a block of active acousto-optical material and operating under Bragg tangential conditions, with the acousto-optical interaction being anisotropic. The devices also include entry and exit faces into this material blocks which are inclined at angles .alpha. and .beta. such that the incoming beam and the emerging beam after the interaction are significantly parallel, keeping operation under Bragg tangential conditions. The devices can also be used to make a spectrum analyzer with a very large number of points and very high dynamics.

Abstract: An optical cache memory architecture is utilized that has the advantages of fast access time, high bandwidth and high density. The optical cache memory architecture stores data holographically with greatly reduced crosstalk and distortions. The memory architecture uses the beam fanning effect present within a high gain photorefractive crystal to eliminate the so-called Bragg degeneracy.

Abstract: The bit line for reading data in or writing data out from a CMOS integrated circuit latch is precharged to the trip point voltage of the latch (as determined by the latch's transistor design) shortly before the occurrence of a read operation. The precharging circuitry uses the latch circuit itself to generate the trip point, hence ensuring that the precharging circuit operates properly with regards to the latch characteristics in spite of temperature, voltage and fabrication process variations. The precharging circuitry ensures that during the operation of reading data from the latch, the bit line voltage never causes the latch to completely switch states, since at most the bit line voltage asymptotically approaches the trip point voltage. The precharging circuit is relatively simple, including only two logic gates and three other transistors.

Abstract: The present invention relates to a memory device having reduced access time of memory cells in a test mode. The memory device forms, in the test mode, read data D.sub.R by applying Ex-OR processing to a plurality of data read from a memory cell array 11 by a data processing circuit 5, to provide the formed data to the outside through a data output circuit 6. The timing of the output of data to the outside is delayed, by delay circuit 12 in the test mode, than that in the normal operation by a time period corresponding to time required for the EX-OR processing in data processing circuit 5. Consequently, output of invalid data to the outside can be prevented, and thus access time of valid data can be reduced.

Abstract: A method for erasing data stored in a non-volatile semiconductor memory is applied to a memory cell transistor including a p-type well region, a source and a drain formed within the p-type well region, and a composite gate including a floating gate electrode formed on the p-type well region. In the method, a plurality of pulses having a high positive voltage is applied to the p-type well region so that a product (I.times.N) of a pulse interval (I) and a number of the plurality of pulses (N) becomes not smaller than 0.1 s on condition that the control gate electrode is fixed to the ground level and the source and drain are kept at a floating state.

Abstract: A semiconductor memory device improves the power source margin without having an extended chip area. The semiconductor memory device of the present invention has a plurality of divided word lines, each having a plurality of drivers for supplying an electric current. The semiconductor memory device includes a boosting circuit for boosting and then supplying an external voltage to the plurality of drivers, and a voltage detection circuit for outputting detection signals which show the results of a comparison made between outputs of the boosting circuit and a reference voltage. The boosting circuit is structured so as to boost the external voltage according to the results of the comparison shown by the detection signals.