Abstract: A stereoviewer and package for facilitating the immediate observation of a stereo pair of photographs and enabling all people to adjust the focal length to their own least distance of distinct vision. A box-shaped main body case for accommodating stereoscopic photographs and a lid case attached to the main body case so as to be slidable thereon serves as a package which is opened and closed by the sliding operation of both cases. A holder portion is provided on the rear surface, for example, of the main body case so as to position and hold the stereoscopic photographs in a standing state, and binocular lenses are disposed on the front surface of the lid case so as to view the stereoscopic photographs therethrough. The rear surface of the main body case and the front surface of the lid case are inclined in such a manner that the side surfaces of the stereoviewer are in a shape of a trapezoid when the main body case is attached upside down to the lid case at the time of observation.

Abstract: An electrically programmable read only memory device stores data bits each in the form of either high or low threshold level of a memory cell, and an accessed data bit is transferred from a selected memory cell to an output data buffer unit for delivery to a destination, wherein a plurality of output data buffer circuits are provided in the output data buffer unit and are selectively used for the data delivery depending upon current driving capability expected by a customer.

Abstract: Disclosed is a semiconductor integrated circuit device, which comprises a booster circuit for boosting a source voltage, a voltage limiter having one end connected to the output terminal of the booster circuit, for limiting the output voltage of the booster circuit to a given value, and a voltage setting circuit, connected to the other end of the voltage limiter, for arbitrarily adjusting a voltage at the other end of the voltage limiter. This design can keep the output voltage of the booster circuit at a constant level and can set that output voltage to an arbitrary voltage.

Abstract: Programmable non-volatile analog voltage source devices and methods wherein analog voltages may be sampled and stored in a non-volatile manner for output, typically through parallel output buffers. In one form and in a single integrated circuit, an input provided to the circuit may be stored at any analog storage location as determined by an address also provided to the circuit, the storage location determining at which of the outputs of the circuit the stored value will appear. While the storage, achieved by way of storage of differential voltages in floating gate MOSFET devices, is non-volatile, the same is also electrically alterable as desired. Various alternate embodiments and methods including the ability to address multiple pages of analog storage locations for storage of analog signals and selective parallel output of each page of the storage, output enable capabilities, parallel inputs and digital inputs are disclosed.

Abstract: A semiconductor integrated circuit is a CAM memory which comprises at least one memory cell including a first storage unit for defining the electrical connection and otherwise the non-connection between a first data line and a match line and a second storage unit for defining the electrical non-connection and otherwise the connection between a second data line and the match line, and a control word line for controlling said first and second storage units in the memory cell, the match line corresponding to at least one of the control word lines, the control word line being used to effect the connection and otherwise non-connection between each of said first and second data lines and the match line in accordance with the definition of connections of said first and second storage units.

Abstract: A FIFO memory circuit with improved read-access time includes an output register, which is connected to the data output terminal of the FIFO. The output register is clocked to provide the output of the FIFO with only the clock-to-output delay of the register. The FIFO memory circuit is formed with a series of latches, each of which latch has a data-input terminal connected in parallel to the data input terminal of the FIFO. Each latch has a tri-state output which is connected to an output terminal for the FIFO. Write-pointers select the next-available one of the FIFO locations to be read into. Read pointers select the next FIFO location to be read from. An input storage register is also provided to improve the input access time of the FIFO.

Abstract: A semiconductor memory device for use in a digital data processor together with a central processing unit (CPU) receives address signals which are validated for a time period n times as long as the machine cycle of the CPU, and it stores therein input data items which are validated for a cycle equal to the machine cycle of the CPU or delivers therefrom output data items which are validated for a cycle equal to the machine cycle of the CPU.

Abstract: A cache memory having rows of memory cells, each row having at least first and second blocks of memory cells. Each memory cell stores a data signal, has at least one word line input, and at least one bit line input/output. A word line connects the word line inputs of at least first, second, third, and fourth memory cells in a row of the cache memory. The first and third memory cells are contained in the first block, while the second and fourth memory cells are contained in the second block. First and second sense amplifiers or write drivers are provided for reading data from or writing data to memory cells. First and second switches having control inputs connect the bit line inputs/outputs of the first and second memory cells, respectively, to the first sense amplifier/write driver. Third and fourth switches having control inputs switchably connect the bit line inputs/outputs of the third and fourth memory cells, respectively, to the second sense amplifier/write driver.

Abstract: The optimum programming voltage in programmable storage arrangements such as EPROMs and notably EEPROMs is dependent on manufacturing tolerances which are difficult to determine from the outside. Therefore, steps are proposed which enable optimum adjustment of the programming voltage by utilizing an additional transistor with a floating gate which is of the same construction as the transistors of the storage cells and which thus also has the same properties in respect of the programming voltage. This additional transistor is connected in series between the high voltage customarily generated on the chip and the programming voltage input of the actual storage matrix. A description is given of a circuit and a sequence of control voltages required by the circuit so as to adjust the additional transistor.

Abstract: A semiconductor mass storage system and architecture can be substituted for a rotating hard disk. The system and architecture avoid an erase cycle each time information stored in the mass storage is changed. (The erase cycle is understood to include, fully programming the block to be erased, and then erasing the block.) Erase cycles are avoided by programming an altered data file into an empty mass storage block rather than over itself as hard disk would. Periodically, the mass storage will need to be cleaned up. Secondly, all blocks in the mass storage are used evenly. These advantages are achieved through the use of several flags, a map to correlate a logical address of a block to a physical address of that block and a count register for each block. In particular, flags are provided for defective blocks, used blocks, old version of a block, a count to determine the number of times a block has been erased and written and erase inhibit flag.

Abstract: The semiconductor memory device according to this invention includes both ROM cells and RAM cells mixed on one line of memory cells. The semiconductor memory device further has a redundant ROM bit line and a redundant RAM bit line. An address on the redundant ROM or RAM bit line is selected in accordance with whether the corresponding address on a defective line to be replaced with the redundant ROM or RAM bit line is a RAM or a ROM. Therefore, it is possible to redundantly recover a defective line including both ROMs and RAMs. Further, a semiconductor memory device including ROMs and RAMs mixedly can be produced in a high yield.

Abstract: There is shortened a test time to ensure data holding power supply voltage. A power supply voltage reduction circuit 3 is provided which reduces power supply voltage Vcc supplied to a power source supply terminal to a predetermined level. Further, a test mode judgement circuit 4 is provided which judges an undergoing test mode to be a data holding power supply voltage test mode and issues an active level test mode signal TM. A switching circuit 5 is further provided which is operable with an output from the power supply voltage reduction circuit 3 as power supply voltage when the test mode signal TM is at an active level to restrict an output data level of said data input buffer circuit 2 and supplies restricted voltage to a memory cell 1 while being operable with the power supply voltage Vcc on the power source supply terminal intactly as the power supply voltage when said signal TM is at an inactive level to supply the output data of the data input buffer circuit 2 to the memeory cell 1.

Abstract: In a semiconductor memory device according to the present invention, the relation between column selection lines and bit line pairs in each memory cell block is defined such that each normal memory cell block and an additional memory cell block share the same column decoder address. Therefore, in a semiconductor memory device having an irregular memory cell array arrangement, it is possible to replace a defective column in any of memory cell blocks by only one type of redundant column.

Abstract: Address pointers (11, 12, 13, 14) include flip-flop circuits and flip-flop circuits including data through circuits. A control circuit (10) controls the flip-flop circuits such that the data through circuits of unnecessary flip-flop circuits cause data to pass through to prevent the flip-flop circuits from selecting unnecessary memory cells (7). The control circuit (10) generates control signals in selection signal producing means including fuses and the like and a decoding portion. Since the decoding portion decodes a flip-flop selection signal, the number of fuses is reduced. This achieves a semiconductor memory comprising address parts for memory cell selection and redundancy circuits which has a reduced area for provision of the fuses for providing redundancy to the semiconductor memory.

Abstract: A ROM IC includes an extra bit line. The extra bit line outputs a first binary logic signal when a word line in a no-use area is attempted to be read and a second binary logic signal when a word line in a use area is attempted to be read. The output of the extra bit line overrides the normal output of the ROM when a word line in a no-use area is attempted to be read, so that the output of a read operation in the no-use area is always a predetermined binary value. This predetermined binary output value occurs in spite of the fact that because of a defect the actual logic value of a storage location in the word line to be read in the no-use area is other than a desired value. When a word line in the use area is read, the output of the extra bit line does not override the actual binary value stored in the word line. Using the extra bit line and associated override circuitry, a ROM IC with a few defects in a no-use area may still be used in an application.

Abstract: A synchronous memory device is provided in which a timing and control circuit (28) receives timing and control inputs. A row address buffer (38) and row decoders (40 and 42) operate to enable rows in plural memory sections (30, 32, 34, and 36). Column decoders (58, 60, 62, and 64) operate to enable columns in each of the memory sections (respectively, 32, 36, 30 and 34). The column decoders (58, 60, 62, and 64) decode addresses received from counters (respectively 52, 54, 48, and 50), an adder (46), and a latch (56). Counters (48, 50, 52, and 54) and adder (46) generate column addresses for each memory section based on a starting address, thereby allowing for internal operation at less than the external system frequency. An operation mode register (29) stores mode data for controlling certain operations, and a state machine (130) operates to prevent indeterminate operation if invalid mode data is input to the operation mode register (29).

Abstract: A semiconductor memory is set in a required operation mode according to an external instruction. The memory properly controls the activation timing of a sense amplifier (1) incorporated in the memory. The memory is capable of surely amplifying a voltage difference between bit lines in every operation mode with no delay in access time, to achieve a high-speed operation.The memory has the sense amplifier (1) for detecting and amplifying a voltage difference between complementary bit lines that transfer data to and from a corresponding memory cell, and a unit (2) for changing the activation timing of the sense amplifier according to an externally instructed operation mode (C).

Abstract: A specialized output buffer circuit which obviates the need to utilize a separate multiplexer to determine polarity selection and output type selection in a programmable logic device is disclosed. In accordance with the present invention, these determinations are made in a specialized output buffer circuit. A sum of product term, a complement of the sum of product term, a registered version of the sum of product term, and a complement of the registered version of the sum of product term, are coupled directly to the output buffer circuit, wherein one of these signals is selected and coupled to an output pin.

Abstract: A mask ROM for storing multi-value data has a memory cell comprising a primary conductive region formed by a first conductive type semiconductor, a source region formed in the primary conductive region by a second conductive type semiconductor, a drain region formed in the primary conductive region by the second conductive type semiconductor, a channel region adjacently formed with the source region and the drain region, a gate insulation layer formed on the channel region, and a gate electrode formed on the gate insulation layer, wherein the channel region or the gate electrode is divided into a plurality of parts, each divided part having a different layer thickness from the other or a different transmissivity for ion injection, so as to form a ROM.

Abstract: Information is optically recorded to a recordable optical disk by a light beam, and a return light is received from the recordable optical disk to produce a tracking error signal. The recordable optical disk includes: a substrate having a disk shape; a groove formed on a surface of the substrate along a predetermined track which the light beam is made to follow; and a recording layer formed on the surface of the substrate, to which the information is recorded by the light beam. A depth of the groove is prescribed such that an amount of the return light from the groove becomes smaller than an amount of the return light from the portion of the recording layer other than the groove in a condition after recording.