Abstract: An improved multilayer electrochromic device, the improvement being to the electrochromic layer which necessarily must include an anion exchanging polymer having a polyoxometallate electrochromic counter ion. An example is the use of PW.sub.12 O.sub.40.sup.3- as the polyoxometallate electrochromic counter ion of an anion exchanging polymer of 90% quaternized 4-vinylpyridine and 10% styrene. Another example is the use of H.sub.2 W.sub.12 O.sub.40.sup.6- as the polyoxometallate electrochromic counter ion of an anion exchanging polymer of 90% protonated 4-vinylpyridine and 10% styrene.

Abstract: A semiconductor memory comprises a dynamic type memory cell array arranged to form a matrix and provided with word lines commonly connected to memory cells of respective columns and bit lines commonly connected to memory cells of respective rows, a dummy cell section having a first set of dummy word lines connected to respective complimentary bit line pairs of said memory cell array by way of respective first capacitances and a second set of dummy word lines connected to respective complementary bit line pairs of said memory cell array by way of respective second capacitances, a dummy word line potential control circuit capable of optionally controlling the mode of driving selected dummy word lines when said word lines of said memory cell array are activated and sense amplifiers connected to the respective complementary bit line pairs of said memory cell array for reading data from selected memory cells of the memory cell array onto the related bit line.

Abstract: A frame assembly for a light shutter including a frame structure for enclosing an electro-optic shutter assembly, the frame structure having a front surface which can be positioned opposite a cover lens, and a switch for controlling an operation mode of the electro-optic shutter assembly, the switch being mounted on the front surface whereby pressure applied to the cover lens activates the switch. The frame assembly can be inserted and used in a welding helmet or other protective eyewear having a standard sized lens aperture.

Abstract: A semiconductor integrated circuit device with a built-in memory circuit group is disclosed, wherein wiring is started from a data terminal position near a data exchange portion of a memory circuit group to reduce the length of a wiring. Accordingly, an operation speed can be improved by the reduction of wiring capacitance and a ratio of unwired wirings can be reduced by reduction of an occupying ratio of wiring channels.

Abstract: The memory ratio is improved and the data holding ability on reading data is enhanced by providing a resistive element between an access transistor and a flip-flop, which form a memory cell of a static memory. Even if the threshold voltage of the access transistor is lowered, the memory cell ratio can be increased. Accordingly, the minimum operating voltage can be lowered and the operating margin for a power source voltage can be increased and simultaneously with this, the soft error immunity can be enhanced. Since the memory cell ratio of the semiconductor memory of the present invention is enhanced by the resistive element, the necessity to preset a lower current drive ability of the access transistor for a drive transistor is decreased. As a result of this, the size of the memory cell can be decreased. Further, the current consumed by the memory cell is decreased by the resistive element.

Abstract: A multi-input memory circuit including a first input gate for selecting one of a plurality of data signals, a first inverting gate for receiving the output of the first input gate as an input, a first feedback gate, which has a structure of a vertical lamination inverter, receives a plurality of clock signals, inverted signals of those clock signals and the output of the first inverting gate, and has its output terminal connected to the output terminal of the first input gate, and a second input gate, which has a vertical lamination inverter structure, and receives a plurality of clock signals, inverted signals of those clock signals and the output of the first input gate, and a second feedback gate, which has a horizontal lamination inverter structure, receives a plurality of clock signals, inverted signals of those clock signals and the output of the second inverting gate, and has its output terminal connected to the output terminal of the second input gate.

Abstract: A segmented focusing mirror having a plurality of segments with each segment having a different focal length is made by constructing a plurality of mirrors with each mirror having a different focal length. The plurality of mirrors are sliced or are cut up into a plurality of segments. One or more segments of one mirror are combined with one or more segments of another mirror to form a master mirror. The master mirror has a common focal point with the segments having different focal lengths. A segmented focusing mirror is replicated from this master mirror by forming a mold of this master mirror and replicating therefrom.

Abstract: The invention relates to memories made in integrated circuit form and, particularly, to high capacity memories that need to have fast access time. The invention provides for carrying out a reading in two stages: precharging and then reading. A precharging is done, at an intermediate value, between the high logic level and the low logic level, of the data output pads at which the information elements read in the memory appear. A circuit to memorize the logic state on the pad and a threshold inverter enable this result to be obtained.

Abstract: The present invention includes an integrated circuit having a self-aligned contact that makes contact to both a region within the substrate and a capacitor plate of a capacitor that is adjacent to the doped region. The present invention also includes a static-random-access memory cell with a capacitor having a first plate and a second plate. The first plate includes a first plate section of a gate electrode of a transistor, and the second plate includes a first conductive member that is substantially coincident with the first plate section. The second plate may be formed over a gate electrode of a latch transistor or over a word line. The disclosure includes methods of forming the integrated circuit and the static-random-access memory cell.

Abstract: In a memory device, data stored in memory cells bridging memory cell columns for two lines can be read out in response to an address signal supplied only once. The memory cells (R00-R03), (R10-R13), (R10-R13), (R20-R23)m (R20-R23) and (R30-R33) for the two adjoining lines are connected to common word lines L0, L1, L2. Also, a series of bit lines are sequentially selected by a counter. The data stored in the memory cells bridging the memory cell columns for the two lines can be read out only once by supplying an address signal only one time.

Abstract: An optical low pass filter including a phase grating for obtaining useful picture image characteristics by provision of preferable low pass effects for each of wave form zones about the spatial frequency components beyond Nyquist limit which are required to be removed as the picture images are discretely sampled in nature in an optical system of a single tube color television camera having a color separating filter, a color video camera using solid state imaging elements, and so on, which is easier in construction to be constructed.

Abstract: A semiconductor memory device operable for reading and writing in a normal mode and in a test mode is divided into memory cell sections each having blocks of memory cells. Data bus lines are connected to the respective blocks, and switches interconnect data bus lines connected to blocks of the different sections. The switch are made conductive during reading and writing in the normal mode and during writing in the test mode, and nonconductive during reading in the test mode. Input data are applied onto the data bus lines connected to one of the blocks for writing in the blocks of the sections simultaneously during writing in the normal mode and in the test mode. In the normal mode, data are read out of the blocks of the sections through the data bus lines connected to the above-mentioned one of the blocks. In the test mode, the data are read out of the blocks of the sections through the data bus lines connected to the respective blocks.

Abstract: An object of the present invention is to provide a semiconductor integrated circuit in which an EEPROM is incorporated in a highly integrated microcomputer having a twin well structure. A twin well region including an n-well region, a p-well region, and a p-type substrate region surrounded by a p-well region are produced in a single semiconductor substrate. A supply voltage system made up of a CPU, a ROM or RAM, a UART, and EEPROM control systems to which the high voltage for the EEPROM is not applied is formed in the twin well region as a CMOS structure, enabling high density integration. A high-voltage system made up of an EEPROM memory cell array and an EEPROM peripheral high-voltage system in the p-type region have an NMOS structure. This arrangement minimizes the substrate effect and enables the high-voltage system to operate normally.

Abstract: A plural port memory system utilizing a memory having a write port and a separate read port wherein the write port includes a write data line, a write address, and a write enable line and wherein the read port includes a read data line, a read address, and a read enable line. The plural port memory system includes: a plurality of interfaces for reading from and writing to the memory, each interface having a read request line and a write request line; and a controller coupled to each of the read and write request lines, and the read and write enable lines for arbitrating access to the memory by the plurality of interfaces.

Abstract: A data bus selector/control amplifier comprises a plurality of basic circuit blocks for controlling the connection of the bus lines of a first data bus comprising a plurality of bus lines and a second data bus comprising a plurality of bus lines. The basic circuit blocks provided correspond to each of the bus lines of the second data bus. Each of the basic circuit blocks sends written data or precharging current to the second data bus via its own data amplifier. Second and third transfer gates retain the data to be written into and data to be read out from the data amplifier.

Abstract: A ferroelectric integrated circuit is provided in which a first layer of conducting lines (14) is formed over an insulating base layer (10). A first ferroelectric layer (16) is formed overlying the first layer of conducting lines (14). A second layer of conducting lines (18) is formed overlying the first ferroelectric layer (16) with each of the conducting lines of the second layer of conducting lines (18) being substantially perpendicular to the conducting lines of the first layer of conducting lines (14). Potentials placed on selected conducting lines in the first and second layers of conducting lines (14 and 18) polarize areas of the first ferroelectric layer (16) between intersections of the selected conducting lines. Multiple layers may be stacked to form a three-dimensional ferroelectric integrated circuit.

Abstract: A semiconductor memory device of the present invention includes a plurality of blocks. Each of the blocks includes: a memory cell group including redundancy cells; a memory cell group selection decoder for, in response to an address signal indicative of an address in the memory cell group, selecting a memory cell having the address; and a redundancy decoder in which any address included in a memory cell group in any one of the blocks except for the block to which the redundancy decoder belongs can be registered, the redundancy decoder outputting a prescribed signal to all of the memory cell group selection decoders in the respective blocks, when the address indicated by the address signal is identical with the registered address.

Abstract: A method and circuit for configuring I/O devices, such as a DRAM or other memory device, uses master-slave buffer circuits in configurable I/O devices. When arranged in a master-slave arrangement, the slave data buffer is adapted to receive both input data and the output of an associated master circuit. In one configuration, each data buffer outputs data based upon the input data. In another configuration, each slave buffer outputs the output of an associated master buffer. The circuit of the present invention is preferably employed with a configurable I/O device incorporated in a lead-on-chip (LOC) package, although could be used in any configurable I/O device.

Abstract: A solid state peripheral storage device in compliance with the PCMCIA standard provides data signals on either 16 data signal lines or 8 data signal lines. The device has a plurality of even number of substantially identical memory integrated circuit chips divided into two groups. Each of the memory integrated circuit chips provides 8 data signal lines divided into two groups of 4 data signal lines. One of the group of 4 data signal lines from one of the group of memory chips is grouped with one of the 4 data signal lines from the other group of memory chips to form a first group of 8 contiguous bus of data signal lines. The other group of 4 data signal lines from one group of memory chips is also collected with 4 data signal lines from the other group of memory chips to form a second group of 8 contiguous data signal lines. The two groups of 8 contiguous data signal lines are grouped together to form the bus of 16 data signal lines.

Abstract: There is provided an improved amplifier circuit responsive to two complementary input signals VI, /VI for providing an amplified output signal VO. In the amplifier circuit, a PMOS transistor and an NMOS transistor alternatingly rendered conductive in response to the input signal VI are connected in series between a power supply potential Vcc and a ground potential. When the input signal VI at a high level is applied, transistor is turned on, while transistor is turned off. Since feedthrough current flowing from the power supply potential towards the ground potential is prevented, the power consumption and operation speed can be improved.