Abstract: Control circuit and control processing for a memory system having a system data bus coupled to at least one data output latch. The control circuit and process generate a read command (RC) to enable the at least one data output latch to latch data from the system data bus in response to a read clock signal (RCLK). The read command (RC) occurs substantially simultaneous with the instant that a valid data state exists on the system data bus and is developed without directly monitoring the system data bus. Upon detecting the read clock signal (RCLK) a latch enable signal is generated. A valid data signal is next generated independent of the system data bus through the use of a dummy circuit having multiple dummy cells, dummy bitlines and a common dummy bus.

Abstract: A DRAM includes a memory cell array having cascade-connected type memory cells arranged in a matrix form and each capable of storing plural-bit information in the unit of bit, sense amplifiers each arranged for a preset number of columns in the memory cell array and disposed in the central portion of the bit lines of the preset number of columns in the arrangement direction, switching circuits disposed on both sides of each of the sense amplifiers, for electrically and selectively connecting the preset number of columns to the sense amplifier, an address designation circuit for separately and serially designating addresses of a plurality of memory cells disposed on both sides of the sense amplifier in the same column of the memory cell array, a word line driving circuit for selectively driving a word line connected to a memory cell of an address designated by the address designation circuit, a column selection circuit for effecting the column selection of the memory cell array, and an access control circuit f

Abstract: A testing circuit for reading and writing a greater number of data bits in parallel during a single clock cycle than through I/O data pins in a memory device. The testing circuit comprises at least one data-in buffer, a plurality of write buffers coupled to the data-in buffer, a plurality of write buses corresponding with the plurality of write buffers and coupled therewith, a plurality of read buses to retrieve data from a plurality of memory cells, a plurality of output buffers corresponding in number with the plurality of read buses and coupled therewith and at least one output driver. Additionally, the method of testing memory basically comprises the steps of inputting at least one data bit having the predetermined polarity into the memory device in order to produce a plurality of data bits having the predetermined polarity. These plurality of data bits are written in parallel into a plurality of memory cells.

Abstract: An insertion device for extracting polarized electromagnetic energy from a beam of particles is disclosed. The insertion device includes four linear arrays of magnets which are aligned with the particle beam. The magnetic field strength to which the particles are subjected is adjusted by altering the relative alignment of the arrays in a direction parallel to that of the particle beam. Both the energy and polarization of the extracted energy may be varied by moving the relevant arrays parallel to the beam direction. The present invention requires a substantially simpler and more economical superstructure than insertion devices in which the magnetic field strength is altered by changing the gap between arrays of magnets.

Abstract: A memory circuit includes a RAM having a memory cell section and a bit manipulation section for controlling a writing of a bit unit to the memory cell section. The RAM is configured to be able to be read and written at different timings by at least two devices. A register stores mask bits for controlling an operation of the bit manipulation section for each bit of data written to the memory cell section. In the bit manipulation operation, a content of a memory cell within the memory cell corresponding to an inactive bit in the register is rewritten by the bit manipulation section, but a content of a memory cell within the memory cell corresponding to the active bit in the register is maintained as it is.

Abstract: A nonvolatile semiconductor memory device using a command control system comprises a protect cell composed of a nonvolatile memory cell, a protect sense amplifier circuit for reading the data from the protect cell, a high-voltage sensing circuit for supplying a voltage during a programmed operation such as a writing or an erasing operation, a protect control circuit for controlling the protect cell, and a control circuit for reading the data from the protect cell and according to the read-out data, controlling the command to the memory cell array.

Abstract: First and second input/output line groups are provided. A plurality of first bit line groups are connected to the first input/output line group through corresponding column selecting circuits, respectively. A plurality of second bit line groups are connected to the second input/output line group through corresponding column selecting circuits, respectively. A column decoder activates one of the column selecting circuits corresponding to the first bit line group and one of the column selecting circuits corresponding to the second bit line group at the same time or with a predetermined time difference.

Abstract: The DRAM according to the present invention comprises so-called cylindrical stacked type capacitors. Each of the cylindrical stacked type capacitors comprises a base portion extending flat on an insulation layer and a surface of a substrate, and a cylindrical portion extending vertically and upwardly from the base portion. Then, the cylindrical portion vertically and upwardly protrudes from an outermost peripheral position of the base portion. As a result, an area where electrodes of the capacitor and capacitance of the capacitor can be increased. Furthermore, with a bit line located below an electrode layer of the capacitor, adjacent capacitors above the bit line can be isolated. Accordingly, it is possible to prevent the bit line contact from defining an isolation distance between the capacitors.

Abstract: A Keplerian zoom finder optical system has an objective lens comprising, in succession from the object side, a first lens unit of negative refractive power, a second lens unit of positive refractive power and a third lens unit of positive refractive power and having positive refractive power as a whole, and an eyepiece of positive refractive power for enlarging and observing the focus image of the objective lens therethrough. The air gap between the first lens unit and the second lens unit is varied to thereby vary finder magnification. The Keplerian zoom finder optical system satisfies a predetermined condition.

Abstract: A four bar linkage (46) supports a head-up-display (HUD) combiner (12) for movement between an upper storage position and a lower operating position. A stop and overcenter mechanism (28a,58;28b,52a;48,52) securely locks the combiner (12) in the operating position. A switch (60) is actuated by the linkage (46) when the combiner (12) is in the operating position.

Abstract: In a semiconductor memory device including memory cells and redundancy memory cells, a redundancy decoder for accessing the redundancy memory cells and disabling a normal decoder for accessing the memory cells includes a test circuit for introducing a test signal into the redundancy decoder. When the test signal is active, the redundancy decoder is disabled in spite of receiving a redundancy address, and instead, the normal decoder is operated to thereby access the memory cells.

Abstract: A semiconductor memory device has a plurality of memory cell arrays; input and output sections each provided so as to correspond to each of the memory cell arrays; and an allocating section provided between the memory cell arrays and the input and output sections, for allocating one of the memory cell arrays to one of the input output sections in ordinary mode, and a plurality of the memory cell arrays to one of the input and output sections in test mode. In the operation test mode, since only a part of the input and output sections are used, it is possible to decrease the number of chips connected to the I/O pins (whose maximum number is limited) of the tester so as to be testable simultaneously, so that the number of chips whose operation tests can be implemented simultaneously can be increased, thus reducing the time required for the operation test of the memory device as a whole.

Abstract: A ferroelectric memory includes a bit line for developing a signal coupled to a ferroelectric memory cell. An integrated load capacitor and sense amplifier are also coupled to the bit line. An isolation circuit is included for selectively electrically isolating the bit line load capacitor from the sense amplifier and ferroelectric memory cell during the active operation of the sense amplifier. The isolation circuit is compatible with both non-volatile ferroelectric and volatile dynamic memory operation.

Abstract: Disclosed is a head shifting apparatus for shifting a head relative to a recording medium, which comprises a shifting mechanism for shifting the head stepwise, detecting means for detecting when the head reaches a predetermined reference position and control means for controlling the shifting mechanism in such a manner that the head is shifted in a first shifting mode where the head is shifted on the basis of a predetermined first unit increment of shifting step until the head reaches the reference position, and after that when to perform normal recording or reproducing, the head is shifted in a second shifting mode where the basis is shifted on the basis of a predetermined second unit increment of shifting step larger than the first unit increment of shifting step.

Abstract: A semiconductor memory device includes a circuit for generating a voltage stress mode signal on the basis of a predetermined signal used in a normal operation of a DRAM circuit, and a control circuit for receiving the test mode signal from the generating circuit and performing control such that, in an AC voltage stress test mode, upper bits, of an output signal from a refresh address counter, which are more significant than a specific bit are fixed at the same level, and lower bits less significant than the specific bit are subjected to a normal count operation and such that, in a DC voltage stress test mode, all the bits of an output signal from the refresh address counter are fixed at the same level so as to cause a word line driving circuit to simultaneously drive all the word lines.

Abstract: A driver circuit for use in a semiconductor memory array is disclosed. The memory array includes a plurality of the driver circuits, each used to drive a word line in the memory array. The driver circuit of the present invention includes a pull up portion and an active pull down portion. The pull up portion includes a pair of cascaded transistors arranged to pull up an output node coupled to the word line. The active pull down portion includes a pair of cascaded transistors arranged to pull down the output node coupled to the word line. A control feedback path is coupled between the output node and the active pull down portion of the driver circuit. The feedback path controls the activation of the pull down portion of the driver circuit.

Abstract: A memory cell data output circuit includes a sense amplifier circuit having a first input terminal supplied with an output signal from memory cells, a second input terminal connected to dummy cells, and an output terminal, first switching element having a gate supplied with a control signal, for switching between the first input terminal and the ground potential, and second switching element having a gate supplied with an inverted signal of the control signal, for switching between the second input terminal and a power source potential, wherein the first and second switching elements respectively set the first and second input terminals to the ground potential and power source potential by turning on the switches in a preset period before the sense amplifier starts the sensing operation according to the control signals and turning off the switches after completion of the preset period.

Abstract: A video RAM having a random access memory, a serial access memory, and a block selector for high speed data processing is disclosed. A serial write transfer operation for transferring data stored in the serial access memory to the random access memory is performed by writing the serial write data on all serial access memory blocks and then transmitting, the serial write data selectively to the desired blocks of the random access memory.

Abstract: A memory is described that includes a main memory array having a plurality of main memory locations and a redundant memory array having a plurality of redundant memory locations. A main decoding circuit is coupled to the main memory array for decoding an address received from an external circuit to access a selected one of the plurality of main memory locations. A storage circuit is provided for pre-storing the address of the selected one of the plurality of main memory locations when the selected one of the plurality of main memory locations is defective. A redundant comparison circuit is coupled to the redundant memory array and the storage circuit for comparing the external address with the address stored in the storage circuit in order to access a selected one of the plurality of redundant memory locations.

Abstract: The present invention has as its subject an electrochromic pane including two glass sheets (1, 2), each coated with a transparent electrically conducting film (3, 4) and separated by an electrode of electrochromic material (5), an electrolyte (6) and a counter-electrode (7). The electrically conducting films (3, 4) are, on the one hand, connected by current supply leads (8, 9) to an electrical supply system generating a potential difference (U.sub.1) according to a desired modification to the coloration of the electrochromic material and, on the other hand, are connected to each other at least at a portion of their periphery by an electrically conducting material (11).