Patents Examined by Evren Seven
  • Patent number: 11522044
    Abstract: Ferroelectric capacitor is formed by conformably depositing a non-conductive dielectric over the etched first and second electrodes, and forming a metal cap or helmet over a selective part of the non-conductive dielectric, wherein the metal cap conforms to portions of sidewalls of the non-conductive dielectric. The metal cap is formed by applying physical vapor deposition at a grazing angle to selectively deposit a metal mask over the selective part of the non-conductive dielectric. The metal cap can also be formed by applying ion implantation with tuned etch rate. The method further includes isotopically etching the metal cap and the non-conductive dielectric such that non-conductive dielectric remains on sidewalls of the first and second electrodes but not on the third and fourth electrodes.
    Type: Grant
    Filed: February 19, 2020
    Date of Patent: December 6, 2022
    Assignee: Kepler Computing Inc.
    Inventors: Gaurav Thareja, Sasikanth Manipatruni, Rajeev Kumar Dokania, Ramamoorthy Ramesh, Amrita Mathuriya
  • Patent number: 11522054
    Abstract: Electrical devices are disclosed. The devices include an insulating substrate. A UO2+x crystal or oriented crystal UO2+x film is on a first portion of the substrate. The UO2+x crystal or film originates and hosts a non-equilibrium polaronic quantum phase-condensate. A first lead on a second portion of the substrate is in electrical contact with the UO2+x crystal or film. A second lead on a third portion of the surface is in electrical contact with the UO2+x crystal or film. The leads are isolated from each other. A UO2+x excitation source is in operable communication with the UO2+x crystal or film. The source is configured to polarize a region of the crystal or film thereby activating the non-equilibrium quantum phase-condensate. One source state causes the UO2+x crystal or film to be conducting. Another source state causes the UO2+x crystal or film to be non-conductive.
    Type: Grant
    Filed: August 24, 2020
    Date of Patent: December 6, 2022
    Assignee: Polaronix Corporation
    Inventor: Steven Conradson
  • Patent number: 11521914
    Abstract: Microelectronic assemblies that include a cooling channel, and related devices and methods, are disclosed herein. For example, in some embodiments, a microelectronic assembly may include a package substrate having a surface, a die having a surface, and a fluidic channel between the surface of the die and the surface of the package substrate, wherein a top surface of the fluidic channel is defined by the surface of the die and a bottom surface of the fluidic channel is defined by the surface of the package substrate. In some embodiments, a microelectronic assembly may include a package substrate having a surface; a die having a surface; and an interposer having a fluidic channel between the surface of the die and the surface of the package substrate.
    Type: Grant
    Filed: December 27, 2018
    Date of Patent: December 6, 2022
    Assignee: Intel Corporation
    Inventors: Zhimin Wan, Cheng Xu, Yikang Deng, Junnan Zhao, Ying Wang, Chong Zhang, Kyu Oh Lee, Chandra Mohan Jha, Chia-Pin Chiu
  • Patent number: 11521057
    Abstract: According to one embodiment of the present disclosure, provided is a learning system that updates a parameter for a neural network, the learning system including: a plurality of differential value calculators; and a parameter update module.
    Type: Grant
    Filed: October 27, 2017
    Date of Patent: December 6, 2022
    Assignees: DENSO IT LABORATORY, INC., TOKYO INSTITUTE OF TECHNOLOGY
    Inventors: Ikuro Sato, Ryo Fujisaki, Akihiro Nomura, Yosuke Oyama, Satoshi Matsuoka
  • Patent number: 11515233
    Abstract: An apparatus includes a semiconductor component and a cooling structure. The cooling structure is over a back side of the semiconductor component. The cooling structure includes a housing, a liquid delivery device and a gas exhaust device. The housing includes a cooling space adjacent to the semiconductor component. The liquid delivery device is connected to an inlet of the housing and is configured to deliver a liquid coolant into the cooling space from the inlet. The gas exhaust device is connected to an outlet of the housing and is configured to lower a pressure in the housing.
    Type: Grant
    Filed: May 8, 2020
    Date of Patent: November 29, 2022
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Tung-Liang Shao, Lawrence Chiang Sheu, Chih-Hang Tung, Chen-Hua Yu, Yi-Li Hsiao
  • Patent number: 11515810
    Abstract: Provided is an energy conversion film excellent in charge retention performance and suppressed in deterioration of piezoelectricity even if it is exposed to a high temperature environment and an energy conversion element and the like using the film. An energy conversion element comprising: an energy conversion film at least comprises a charged resin film consisting of a resin film at least containing a thermoplastic resin and a metal soap; and an electrode provided on at least one of the two surfaces of the energy conversion film.
    Type: Grant
    Filed: January 31, 2018
    Date of Patent: November 29, 2022
    Assignee: YUPO CORPORATION
    Inventors: Hiroshi Koike, Yutaro Sugamata, Seiichiro Iida
  • Patent number: 11515463
    Abstract: An optical element includes a primary electrode, a secondary electrode overlapping at least a portion of the primary electrode, and an electrostrictive ceramic layer disposed between and abutting the primary electrode and the secondary electrode, where the electrostrictive ceramic may be characterized by a relative density of at least approximately 99%, an average grain size of at least approximately 300 nm, a transmissivity within the visible spectrum of at least approximately 70%, and bulk haze of less than approximately 10%. Optical properties of the electrostrictive ceramic may be substantially unchanged during the application of a voltage to the electrostrictive ceramic layer and the attendant actuation of the optical element.
    Type: Grant
    Filed: August 29, 2019
    Date of Patent: November 29, 2022
    Assignee: Meta Platforms Technologies, LLC
    Inventors: Spencer Allan Wells, Katherine Marie Smyth, Andrew John Ouderkirk
  • Patent number: 11502216
    Abstract: A method of manufacturing a photo sensor includes forming a first conductive layer on a substrate, the first conductive layer including a metal layer and a transparent conductive oxide layer formed on the metal layer, forming a photoconductive layer on the first conductive layer, forming a second conductive layer on the photoconductive layer, forming a first photoresist pattern on the second conductive layer, etching the second conductive layer using the first photoresist pattern as an etch mask to form a second electrode, deforming the first photoresist pattern to form a second photoresist pattern, and etching the photoconductive layer and the first conductive layer using the second photoresist pattern to form a photoconductive pattern and a first electrode, respectively.
    Type: Grant
    Filed: May 29, 2020
    Date of Patent: November 15, 2022
    Assignee: SAMSUNG DISPLAY CO., LTD.
    Inventors: Woo-Seok Jeon, Kwang Hyun Kim, Heon Sik Ha
  • Patent number: 11475276
    Abstract: A generative network may be learned in an adversarial setting with a goal of modifying synthetic data such that a discriminative network may not be able to reliably tell the difference between refined synthetic data and real data. The generative network and discriminative network may work together to learn how to produce more realistic synthetic data with reduced computational cost. The generative network may iteratively learn a function that synthetic data with a goal of generating refined synthetic data that is more difficult for the discriminative network to differentiate from real data, while the discriminative network may be configured to iteratively learn a function that classifies data as either synthetic or real. Over multiple iterations, the generative network may learn to refine the synthetic data to produce refined synthetic data on which other machine learning models may be trained.
    Type: Grant
    Filed: November 6, 2017
    Date of Patent: October 18, 2022
    Assignee: Apple Inc.
    Inventors: Ashish Shrivastava, Tomas J. Pfister, Cuneyt O. Tuzel, Russell Y. Webb, Joshua Matthew Susskind
  • Patent number: 11476118
    Abstract: A method for manufacturing a nanowire includes providing a sacrificial substrate, providing a patterned mask layer on the sacrificial substrate, providing a nanowire on the sacrificial substrate through an opening in the patterned mask layer, and removing the sacrificial substrate. Because the sacrificial substrate is used for growing the nanowire and later removed, the material of the sacrificial substrate can be chosen to be lattice matched with the material of the nanowire without regard to the electrical properties thereof. Accordingly, a high-quality nanowire can be grown and operated without the degradation in performance normally experienced when using a lattice matched substrate.
    Type: Grant
    Filed: February 25, 2020
    Date of Patent: October 18, 2022
    Assignee: Microsoft Technology Licensing, LLC
    Inventors: Geoffrey C. Gardner, Raymond L. Kallaher, Sergei V. Gronin
  • Patent number: 11450583
    Abstract: Provided is a stacked semiconductor package including a package base substrate including a plurality of signal wires and at least one power wire, wherein a plurality of top downsurface connecting pads and a plurality of bottom surface connecting pads are on a top surface and a bottom surface of the package base substrate, respectively; and a plurality of semiconductor chips that are sequentially stacked on the package base substrate and are electrically connected to the top surface connecting pads, the plurality of semiconductor chips including a first semiconductor chip that is a bottommost semiconductor chip, and a second semiconductor chip that is on the first semiconductor chip, wherein the signal wires are arranged apart from a portion of the package base substrate, the first portion that overlaps a first edge of the first semiconductor chip, the first edge overlapping the second semiconductor chip in a vertical direction.
    Type: Grant
    Filed: March 26, 2019
    Date of Patent: September 20, 2022
    Assignee: Samsung Electronics Co., Ltd.
    Inventor: Keun-Ho Choi
  • Patent number: 11450571
    Abstract: Methods of manufacturing a semiconductor structure are provided. One of the methods includes: receiving a substrate including a first conductive region of a first transistor and a second conductive region of a second transistor, wherein the first transistor and the second transistor have different conductive types; performing an amorphization on the first conductive region and the second conductive region; performing an implantation over the first conductive region of the first transistor; forming a contact material layer over the first conductive region and the second conductive region; performing a thermal anneal on the first conductive region and the second conductive region; and performing a laser anneal on the first conductive region and the second conductive region.
    Type: Grant
    Filed: May 6, 2019
    Date of Patent: September 20, 2022
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY LTD.
    Inventors: Chun Hsiung Tsai, Cheng-Yi Peng, Ching-Hua Lee, Chung-Cheng Wu, Clement Hsingjen Wann
  • Patent number: 11444215
    Abstract: A device and method for fabricating a photovoltaic device includes forming a double layer transparent conductive oxide on a transparent substrate. The double layer transparent conductive oxide includes forming a doped electrode layer on the substrate, and forming a buffer layer on the doped electrode layer. The buffer layer includes an undoped or p-type doped intrinsic form of a same material as the doped electrode layer. A light-absorbing semiconductor structure includes a p-type semiconductor layer on the buffer layer, an intrinsic layer and an n-type semiconductor layer.
    Type: Grant
    Filed: January 13, 2020
    Date of Patent: September 13, 2022
    Assignees: INTERNATIONAL BUSINESS MACHINES CORPORATION, BAY ZU PRECISION CO., LTD.
    Inventors: Shun-Ming Chen, Chien-Chih Huang, Joel P. Desouza, Augustin J. Hong, Jeehwan Kim, Chien-Yeh Ku, Devendra K. Sadana, Chuan-Wen Wang
  • Patent number: 11437599
    Abstract: The present disclosure provides a display panel and a display device. The display panel includes a substrate, including a display area and a non-display area; a display functional layer disposed on the display area; a plurality of protruding blocks disposed on the non-display area; and an encapsulation layer disposed on the display functional layer; wherein the encapsulation layer extends along an edge of the display functional layer to the non-display area and covers the plurality of protruding blocks.
    Type: Grant
    Filed: October 23, 2019
    Date of Patent: September 6, 2022
    Assignee: WUHAN CHINA STAR OPTOELECTRONICS SEMICONDUCTOR DISPLAY TECHNOLOGY CO., LTD.
    Inventor: Shaojing Wu
  • Patent number: 11429405
    Abstract: Method and apparatus for providing personalized self-help experience in online application. A predictive model is trained to learn a relationship between one or more user features and one or more tags using historical user feature data. High-dimensional vectors representing each of a plurality of questions are generated and stored in the lookup table. The trained predictive model outputs tags probabilities from the incoming user data, using the learned relationship. A user high-dimensional vector is formed based on the tags probabilities. Similarity metrics are calculated between the high-dimensional vector for the respective question and the user high dimensional vector. One or more of the most relevant question titles are returned to a client device for presentation to a user.
    Type: Grant
    Filed: November 28, 2017
    Date of Patent: August 30, 2022
    Assignee: INTUIT, INC.
    Inventors: Madelaine Daianu, Yao Morin, Ling Feng Wei, Chris Peters, Itai Jeczmien
  • Patent number: 11430861
    Abstract: Ferroelectric capacitor is formed by conformably depositing a non-conductive dielectric over the etched first and second electrodes, and forming a metal cap or helmet over a selective part of the non-conductive dielectric, wherein the metal cap conforms to portions of sidewalls of the non-conductive dielectric. The metal cap is formed by applying physical vapor deposition at a grazing angle to selectively deposit a metal mask over the selective part of the non-conductive dielectric. The metal cap can also be formed by applying ion implantation with tuned etch rate. The method further includes isotopically etching the metal cap and the non-conductive dielectric such that non-conductive dielectric remains on sidewalls of the first and second electrodes but not on the third and fourth electrodes.
    Type: Grant
    Filed: December 27, 2019
    Date of Patent: August 30, 2022
    Assignee: Kepler Computing Inc.
    Inventors: Gaurav Thareja, Sasikanth Manipatruni, Rajeev Kumar Dokania, Ramamoorthy Ramesh, Amrita Mathuriya
  • Patent number: 11429915
    Abstract: Systems and methods for predicting feature values in a matrix are disclosed. In example embodiments, a server accesses a matrix, the matrix having multiple dimensions, one dimension of the matrix representing features, and one dimension of the matrix representing entities. The server separates the matrix into multiple submatrices along a first dimension, each submatrix including all cells in the matrix for a set of values in the first dimension. The server provides the multiple submatrices to multiple machines. The server computes, using each machine, a correlation between values in at least one second dimension of the matrix and a value for a preselected feature in the matrix, the correlation being used to predict the value for the preselected feature based on other values along the at least one second dimension. The server provides an output representing the computed correlation.
    Type: Grant
    Filed: November 30, 2017
    Date of Patent: August 30, 2022
    Assignee: Microsoft Technology Licensing, LLC
    Inventors: Gio Borje, Benjamin John McCann, David DiCato, Jerry Lin, Skylar Payne, Apoorv Khandelwal, Nadeem Anjum
  • Patent number: 11424376
    Abstract: A superlattice absorber for a detector is provided. The superlattice absorber includes a plurality of material periods deposited successively. Each of the material periods includes a first layer of InAs, InGaAs, InAsSb or InGaAsSb; and a plurality of second layers of InGaAsSb. The second layers comprise at least two InGaAsSb layers with at least two different content combinations. The content of the second layers is different from that of the first layer.
    Type: Grant
    Filed: April 9, 2019
    Date of Patent: August 23, 2022
    Inventor: Peng Du
  • Patent number: 11423259
    Abstract: A system that can create an approximated model from a trained machine learning model (such as a neural network) where the approximated model can operate using fewer computing resources than the original trained model. The system can create the approximated model without the voluminous training data used to create the original trained model. The system can rely on just the data describing the trained model and an indicator as to how closely the approximated model should correspond to the original model and/or the desired savings of computing resources. Various lossless and/or lossy approximations may be performed to obtain multiple approximated models that may be substituted for the trained model during runtime operations to achieve significant speed/cost savings over operation of the original trained model.
    Type: Grant
    Filed: December 12, 2017
    Date of Patent: August 23, 2022
    Assignee: Amazon Technologies, Inc.
    Inventors: Michele Pratusevich, Jeremy Samuel De Bonet
  • Patent number: 11417596
    Abstract: In some embodiments, the present disclosure relates to an integrated chip that includes an insulator layer arranged over a substrate. Further, an upper routing structure is arranged over the insulator layer and is made of a semiconductor material. A lower optical routing structure is arranged below the substrate and is embedded in a lower dielectric structure. The integrated chip further includes an anti-reflective layer that is arranged below the substrate and directly contacts the substrate.
    Type: Grant
    Filed: August 4, 2020
    Date of Patent: August 16, 2022
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Weiwei Song, Chan-Hong Chern, Feng-Wei Kuo, Lan-Chou Cho, Stefan Rusu