Patents Examined by Evren Seven
  • Array substrate and manufacturing method thereof, display panel and display device
    Patent number: 11296123
    Abstract: An array substrate and a manufacturing method thereof, a display panel and a display device are provided. The array substrate includes common electrodes, multiple first common electrode lines and multiple second common electrode lines. The multiple first common electrode lines intersect with the multiple second common electrode lines to form grids. The multiple first common electrode lines are connected with the common electrodes through first via-holes and the multiple second common electrode lines are connected with the common electrodes through second via-holes.
    Type: Grant
    Filed: September 29, 2017
    Date of Patent: April 5, 2022
    Assignees: BOE TECHNOLOGY GROUP CO., LTD., BEIJING BOE DISPLAY TECHNOLOGY CO., LTD.
    Inventors: Ning Zhu, Qiujie Su, Chongyang Zhao
  • Package structure
    Patent number: 11282766
    Abstract: A package structure including a reconstructed wafer, a heat dissipation substrate, a semiconductor device, and a fixing mechanism is provided. The heat dissipation substrate is disposed on a side of the reconstructed wafer and includes an inlet, a base plate located between the inlet and the reconstructed wafer, and a connection member located and coupled between the inlet and the base plate. The connection member has an inclined fluid channel that descends from the inlet to the base plate. The semiconductor device is disposed on another side of the reconstructed wafer, wherein the heat dissipation substrate and the semiconductor device are respectively located on opposite sides of the reconstructed wafer. The fixing mechanism fixes the reconstructed wafer, the heat dissipation substrate, and the semiconductor device together.
    Type: Grant
    Filed: January 8, 2020
    Date of Patent: March 22, 2022
    Assignee: Taiwan Semiconductor Manufacturing Company
    Inventors: Shih-Chang Ku, Wensen Hung, Hung-Chi Li
  • Array substrate, manufacturing method, display panel and display device thereof
    Patent number: 11276713
    Abstract: Arrangements disclosed in the present disclosure provide an array substrate, a manufacturing, a display panel and a display device. The array substrate comprises: a first signal line comprising a first extension portion along a first direction and a first connection portion along a second direction, which is provided with via holes; a second signal line comprising a second extension portion and a second connection portion along the second direction, which is provided with via holes; and a conductive connection layer, configured to connect the first signal line and the second signal line through the via holes of the first connection portion and second connection portion. The first connection portion and the second connection portion are lined up in a direction perpendicular to the second direction.
    Type: Grant
    Filed: April 4, 2019
    Date of Patent: March 15, 2022
    Assignees: Beijing BOE Technology Development Co., Ltd., BOE Technology Group Co, , Ltd.
    Inventors: Pan Li, Yong Qiao
  • Array substrate, OLED display panel and display device
    Patent number: 11271187
    Abstract: Array substrate, an organic light emitting diode (OLED) display panel and a display device are provided with a flexible substrate, an water- and oxygen-resistant layer, a signal line layer and a flattening layer that are laminated in a bending region of the array substrate, signal transmission lines formed by patterning the signal line layer are formed on the water- and oxygen-resistant layer. By manufacturing the signal line layer of the bending region on the water- and oxygen-resistant layer and filling with the flattening layer, the problem of electrical performance of signal lines, caused by water and oxygen permeating the signal line layer through organic photoresist, is alleviated.
    Type: Grant
    Filed: November 5, 2019
    Date of Patent: March 8, 2022
    Assignee: WUHAN CHINA STAR OPTOELECTRONICS SEMICONDUCTOR DISPLAY TECHNOLOGY CO., LTD.
    Inventors: Ding Ding, Liang Fang
  • Semiconductor device and method of manufacturing the same
    Patent number: 11264380
    Abstract: A semiconductor device includes a substrate, a first active fin, a second active fin, a dummy fin and a first gate structure. The first and the second active fin are on the substrate and extend along a first direction. The dummy fin is disposed between the first active fin and the second active fin, and extends in the first direction. The dummy fin includes a plurality of layers, and each of the layers includes a material different from another layer. The first gate structure crosses over the dummy fin, the first and the second active fins.
    Type: Grant
    Filed: August 27, 2018
    Date of Patent: March 1, 2022
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
    Inventors: Hou-Ju Li, Chur-Shyang Fu, Chun-Sheng Liang, Jeng-Ya David Yeh
  • Method of manufacturing a semiconductor device, and associated semiconductor device and system
    Patent number: 11257670
    Abstract: A method of manufacturing a semiconductor device, including: providing a substrate including a first cell and a second cell that are arranged in a first direction; forming a plurality of first metal strips extending in the first direction and arranged in a second direction on a first plane; forming a first trench over a boundary between the first cell and the second cell, wherein a bottom surface of the first trench is on a second plane over the first plane; filling the first trench with a non-conductive material, resulting in a separating wall which extends in the first direction; and forming a plurality of second metal strips extending in the second direction on a third plane over the second plane, wherein a first second metal strip and a second second metal strip separated from each other by the separating wall; wherein the second direction is orthogonal to the first direction.
    Type: Grant
    Filed: February 10, 2020
    Date of Patent: February 22, 2022
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY LTD.
    Inventors: Shih-Wei Peng, Chia-Tien Wu, Jiann-Tyng Tzeng
  • Semiconductor structure and method for fabricating the same
    Patent number: 11257752
    Abstract: A semiconductor structure and a method of fabricating the same is disclosed. The semiconductor device includes a conductive structure that comprises: an upper conductive line arranged above and in electrical connection with a circuit component in a lower device layer through a via plug, wherein the upper conductive line extends laterally over the via plug; an interposing layer having a substantially uniform thickness arranged between the via plug and the upper conductive line, and extending laterally beyond a planar projection of the via plug, wherein the upper conductive line is in electrical connection with the via plug through the interposing layer; and an overlayer is disposed over the upper conductive line.
    Type: Grant
    Filed: December 5, 2019
    Date of Patent: February 22, 2022
    Assignee: XIA TAI XIN SEMICONDUCTOR (QING DAO) LTD.
    Inventors: Hyunyoung Kim, Dowon Kwak, Kang-Won Seo
  • High-k dielectric materials comprising zirconium oxide utilized in display devices
    Patent number: 11239258
    Abstract: Embodiments of the disclosure generally provide methods of forming a capacitor layer or a gate insulating layer with high dielectric constant as well as low film current leakage and desired film qualities for display applications. In one embodiment, a thin film transistor structure includes a dielectric layer formed on a substrate, wherein the dielectric layer is a zirconium containing material comprising aluminum, and gate, source and drain electrodes formed on the substrate, wherein the gate, source and drain electrodes formed above or below the dielectric layer.
    Type: Grant
    Filed: July 11, 2017
    Date of Patent: February 1, 2022
    Assignee: Applied Materials, Inc.
    Inventors: Xiangxin Rui, Lai Zhao, Jrjyan Jerry Chen, Soo Young Choi, Yujia Zhai
  • Semiconductor device and method for fabricating the same
    Patent number: 11217594
    Abstract: The present application discloses a semiconductor device and a method for fabricating the semiconductor device. The semiconductor device includes a substrate, a low-level bit line positioned above the substrate, a high-level bit line bottom contact positioned above the substrate and adjacent to the low-level bit line, and first air gaps positioned adjacent to the low-level bit line.
    Type: Grant
    Filed: September 5, 2019
    Date of Patent: January 4, 2022
    Assignee: NANYA TECHNOLOGY CORPORATION
    Inventor: Tse-Yao Huang
  • Display panel
    Patent number: 11217521
    Abstract: The invention provides a display panel including a display area and a non-display area, wherein the non-display area is provided with a plurality of signal transmission lines, and the non-display area includes a bending region on a side of the display area. In the bending region, at least one hole is disposed at intervals on one of the signal transmission lines and the hole is filled with a high ductility metal.
    Type: Grant
    Filed: October 14, 2019
    Date of Patent: January 4, 2022
    Inventor: Xia Chen
  • Display panel, manufacturing method thereof, and display device
    Patent number: 11217642
    Abstract: A display panel and a method of manufacturing the display panel are provided. The display panel includes an array substrate, a planarization layer, a pixel defining layer, an organic light emitting device, and an inorganic layer disposed between the planarization layer and the pixel defining layer to block moisture and oxygen. An encapsulation structure of the array substrate is cooperatively formed by a combination of a first interlayer dielectric layer contained in a thin-film transistor, the planarization layer, and the inorganic layer.
    Type: Grant
    Filed: April 16, 2019
    Date of Patent: January 4, 2022
    Assignee: Wuhan China Star Optoelectronics Semiconductor Display Technology Co., Ltd.
    Inventor: Ao Wang
  • Evaluation method on anion permeability of graphene-containing membrane and photoelectric conversion device
    Patent number: 11217714
    Abstract: The present embodiment provide a method for evaluating anion permeability of a graphene-containing membrane and also to provide a photoelectric conversion device employing a graphene-containing membrane having controlled anion permeability.
    Type: Grant
    Filed: March 13, 2020
    Date of Patent: January 4, 2022
    Assignees: KABUSHIKI KAISHA TOSHIBA, TOSHIBA ENERGY SYSTEMS & SOLUTIONS CORPORATION
    Inventors: Katsuyuki Naito, Naomi Shida, Yutaka Saita
  • Face-up fan-out electronic package with passive components using a support
    Patent number: 11211337
    Abstract: A face-up fan-out electronic package including at least one passive component located on a support. The electronic package can include a die. The die can include a plurality of conductive pillars having a proximal end communicatively coupled to the first side of the die and a distal end opposite the proximal end. A mold can at least partially surround the die. The mold can include a first surface that is coplanar with the distal end of the conductive pillars and a second surface opposing the first surface. In an example, the passive component can include a body and a lead. The passive component can be located within the mold. The lead can be coplanar with the first surface, and the body can be located at a distance from the second surface. The support can be located between the body and the second surface.
    Type: Grant
    Filed: December 4, 2019
    Date of Patent: December 28, 2021
    Assignee: Intel Corporation
    Inventors: Lizabeth Keser, Thomas Ort, Thomas Wagner, Bernd Waidhas
  • Short wavelength infrared optoelectronic devices having graded or stepped dilute nitride active regions
    Patent number: 11211514
    Abstract: Semiconductor optoelectronic devices having a dilute nitride active region are disclosed. In particular, the semiconductor devices have a dilute nitride active region with at least two bandgaps within a range from 0.7 eV and 1.4 eV. Photodetectors comprising a dilute nitride active region with at least two bandgaps have a reduced dark current when compared to photodetectors comprising a dilute nitride active region with a single bandgap equivalent to the smallest bandgap of the at least two bandgaps.
    Type: Grant
    Filed: March 5, 2020
    Date of Patent: December 28, 2021
    Assignee: ARRAY PHOTONICS, INC.
    Inventors: Ferran Suarez, Ding Ding, Aymeric Maros
  • Semiconductor device and fabrication method thereof
    Patent number: 11205572
    Abstract: Fabrication method of a semiconductor device is provided. The method includes forming an etch layer on the substrate, forming a first transitional layer and a first barrier layer on the etch layer, forming first islands on the first transitional layer by patterning the first barrier layer, forming first trenches in the first transitional layer to expose the etch layer, transferring the pattern of the first trenches into the etch layer and removing the first island, forming a second transitional layer and a second barrier layer on the etch layer and the first trenches, forming second islands on the second transitional layer by patterning the second barrier layer, forming second trenches in the second transitional layer to expose the etch layer, and transferring the pattern of the second trenches into the etch layer.
    Type: Grant
    Filed: March 20, 2020
    Date of Patent: December 21, 2021
    Assignees: Semiconductor Manufacturing International (Shanghai) Corporation, Semiconductor Manufacturing International (Beijing) Corporation
    Inventors: Zhi Dong Wang, Yi Ying Zhang
  • Methods for forming memory devices, and associated devices and systems
    Patent number: 11201083
    Abstract: Methods of manufacturing memory devices having memory cells and corresponding selectors, and associated systems and devices, are disclosed herein. In one embodiment, a method of manufacturing a memory device includes (a) removing a protection layer formed over the memory cells and (b) forming a cap layer over the memory cells before forming a conductive via through the memory device. The cap layer is configured to protect the memory cells during operation and can comprise a resistive material. The protection layer can be more efficiently removed with improved process margin and less device health impact using a polishing process before the conductive via is formed, thus increasing the manufacturing margin of the memory device.
    Type: Grant
    Filed: February 3, 2020
    Date of Patent: December 14, 2021
    Assignee: Micron Technology, Inc.
    Inventors: Jukuan Zheng, Sri Sai Sivakumar Vegunta, Kevin L. Baker, Josiah Jebaraj Johnley Muthuraj, Efe S. Ege
  • (GaMe)Oternary alloy material, its preparation method and application in solar-blind ultraviolet photodetector
    Patent number: 11201254
    Abstract: A (GaMe)2O3 ternary alloy material, its preparation method and application in a solar-blind ultraviolet photodetector are provided. The (GaMe)2O3 ternary alloy material of the present invention is formed by solid solution of Ga2O3 and Me2O3 in a molar ratio of 99:1 to 50:50, wherein the Me is any one of Lu, Sc, or Y. The (GaMe)2O3 ternary alloy material of the present invention can be used to prepare the active layer of a solar-blind ultraviolet photodetector. In the present invention, the band gap of Me2O3 is higher than that of Ga2O3, and Ga3+ ions in Ga2O3 are partially replaced by Me3+ ions to obtain a higher band gap (GaMe)2O3 ternary alloy material to reduce the dark current of the device and promote the blue shift of the cut-off wavelength to within 280 nm.
    Type: Grant
    Filed: April 22, 2020
    Date of Patent: December 14, 2021
    Assignee: HUBEI UNIVERSITY
    Inventors: Yunbin He, Mingkai Li, Pan Huang, Qile Wang, Yinmei Lu, Gang Chang, Pai Li
  • Semiconductor device, high-frequency power amplifier, and method of manufacturing semiconductor device
    Patent number: 11195807
    Abstract: Reduction in impedance in a lead connected to a semiconductor element is achieved while achieving anchor effect. The semiconductor device includes a heatsink, a semiconductor element, a lead disposed on an upper side of the heatsink, and a molding material formed to cover the lead, the heatsink, and the semiconductor element. Formed on an edge portion of a lower surface in a position, in the heatsink, overlapping with the lead in a plan view is a first convex portion protruding more than an edge portion of an upper surface in the position, and formed on an edge portion of an upper surface in a position, in the heatsink, which does not overlap with the lead in a plan view is a second convex portion protruding more than an edge portion of a lower surface in the position.
    Type: Grant
    Filed: September 28, 2017
    Date of Patent: December 7, 2021
    Assignee: Mitsubishi Electric Corporation
    Inventors: Tomoyuki Asada, Yoichi Nogami, Kenichi Horiguchi, Shigeo Yamabe, Satoshi Miho, Kenji Mukai
  • Semiconductor module and method of evaluating semiconductor module
    Patent number: 11195777
    Abstract: An object is to provide a semiconductor module that ensures to determine a state of the thermally conductive material provided between a semiconductor device and a heat sink. The semiconductor module includes the semiconductor device, the thermally conductive material, and a controller. The thermally conductive material has a property of softening or melting at a specific temperature and is provided on one surface, which is mountable on the heat sink, of the outer surfaces of the semiconductor device. The controller determines the state of the thermally conductive material between the one surface of the semiconductor device and the heat sink based on temperature information on two different points in the semiconductor device.
    Type: Grant
    Filed: December 23, 2019
    Date of Patent: December 7, 2021
    Assignee: Mitsubishi Electric Corporation
    Inventor: Hiroaki Nagafuchi
  • Radio frequency (RF) module using a tunable RF filter with non-volatile RF switches
    Patent number: 11196401
    Abstract: In tuning a radio frequency (RF) module including a non-volatile tunable RF filter, a desired frequency and an undesired frequency being provided by an amplifier of the RF module are detected. The non-volatile tunable RF filter is coupled to an output of the amplifier of the RF module. A factory setting of an adjustable capacitor in the non-volatile tunable RF filter is changed by factory-setting a state of a non-volatile RF switch, such that the non-volatile tunable RF filter substantially rejects the undesired frequency and substantially passes the desired frequency. The adjustable capacitor includes the non-volatile RF switch, and the factory setting of the adjustable capacitor corresponds to a factory-set state of the non-volatile RF switch. An end-user is prevented access to the non-volatile RF switch, so as prevent the end-user from modifying the factory-set state of the non-volatile RF switch.
    Type: Grant
    Filed: May 22, 2019
    Date of Patent: December 7, 2021
    Assignee: Newport Fab, LLC
    Inventors: Chris Masse, David J. Howard, Nabil El-Hinnawy, Gregory P. Slovin