Abstract: A nonvolatile memory device includes a memory cell region including first metal pads, and a peripheral circuit region. The peripheral circuit region includes second metal pads, a signal storage circuit that stores control signals and a data signal received from external of the nonvolatile memory device, a debugging information generator that generates debugging information based on the stored control signals and the stored data signal, and a debugging information register that outputs the debugging information in response to a debugging information external of the nonvolatile memory device. The peripheral circuit region is vertically connected to the memory cell region by the first metal pads and the second metal pads.

Abstract: A flash memory system may include a flash memory and a circuit for decoding a result of a read operation on the flash memory using a first codeword. The circuit may be configured to generate first soft information of the first codeword. The circuit may be further configured to generate second soft information of a second codeword. The circuit may be configured to generate third soft information based on the first soft information and the second soft information. The circuit may be configured to decode the result of the read operation on the flash memory using the third soft information.

Abstract: Various implementations described herein relate to systems and methods for encoding and decoding data having input payload stored in a non-volatile storage device, including encoding the input payload by concatenating a plurality of short codewords to generate a plurality of encoded short codewords, and decoding the plurality of encoded short codewords to obtain the data, where each of the plurality of short codewords corresponding to a portion of the input payload.

Abstract: An apparatus includes a central processing unit (CPU) core and a cache subsystem coupled to the CPU core. The cache subsystem includes a memory configured to store a line of data and an error correcting code (ECC) syndrome associated with the line of data, where the ECC syndrome is calculated based on the line of data and the ECC syndrome is a first type ECC. The cache subsystem also includes a controller configured to, in response to a request from a master configured to implement a second type ECC, the request being directed to the line of data, transform the first type ECC syndrome for the line of data to a second type ECC syndrome send a response to the master. The response includes the line of data and the second type ECC syndrome associated with the line of data.

Abstract: A hard-decision (HD) forward error correcting (FEC) coded signal is decoded by a decoder to produce decoded bits using marked reliable bits of the HD-FEC coded signal and marked unreliable bits of the HD-FEC coded signal. The marked reliable and unreliable bits are computed by calculation and marking blocks based on an absolute value of log-likelihood ratios of the HD-FEC coded signal. The HD-FEC coded signal may be, for example, a staircase code coded signal or a product code coded signal.

Abstract: A memory system includes a memory device and a controller. The memory device includes a plurality of non-volatile memory groups individually storing a plurality of data segments, each data segment corresponding to a codeword. The controller is configured to perform hard decision decoding to correct an error when the error is included in a first data segment among the plurality of data segments, determine whether other data segments associated with the first data segment, among the plurality of data segments, are readable when the hard decision decoding fails, and perform chipkill decoding based on the first data segment and the other data segments when the other data segments are readable.

Abstract: Initialization stripes of a redundant array of inexpensive disks (RAID) may include determining whether the stripes have already been initialized based on redundant correction information. Further, un-initialized stripes may be initialized before intended if write requests are received for such un-initialized stripes. Still further, rebuilt stripes (e.g., portions thereof) may also be checked to determine whether such rebuilt stripes have been initialized based on error detection codes.

Abstract: A sorting device and method for determining elementary check node components in an elementary check node processor implemented in a non-binary error correcting code decoder by sorting auxiliary components are presented. The auxiliary components are stored in a plurality of FIFO memories, each FIFO memory being assigned a FIFO number index. Each auxiliary component stored in a given FIFO memory comprises an auxiliary symbol, a reliability metrics representing the reliability of the auxiliary symbol, and the FIFO number index assigned to the given FIFO memory. The sorting device is configured to sort the auxiliary components by a plurality of multiplexers arranged sequentially. Each multiplexer is configured to initialize a candidate elementary check node component from the components of a FIFO memory corresponding to the auxiliary component which comprise the most reliable auxiliary symbol and to perform one or more iterations of the illustrated receiving, updating and sorting steps.

Abstract: According to one embodiment, a storage device includes a nonvolatile memory and a control circuit. The nonvolatile memory includes a plurality of storage blocks, each including a shift register. The control circuit controls writing and reading of data to and from the nonvolatile memory. The control circuit is configured to: read target data from a first storage block of the plurality of storage blocks; and write the target data read from the first storage block to a second storage block of the plurality of storage blocks, the second storage block being different from the first storage block.

Abstract: A low-density parity check (LDPC) decoder includes a variable node unit (VNU) comprising a plurality of variable nodes configured to perform sums. A first message mapper of the LDPC decoder receives first n1-bit indices from likelihood ratio (LLR) input and maps the first n1-bit indices to first numerical values that are input to the variable nodes of the VNU. A second message mapper of the LDPC decoder receives second n2-bit indices from a check node unit (CNU) and maps the second n2-bit indices to second numerical values that are input to the variable nodes of the VNU. The CNU includes a plurality of check nodes that perform parity check operations. The first and second numerical values having ranges that are larger than what can be represented in n1-bit and n2-bit binary, respectively.

Abstract: Methods, systems, and apparatuses for a memory device (e.g., DRAM) including an error check and scrub (ECS) procedure in conjunction with refresh operations are described. The ECS procedure may include read/modify-write cycles when errors are detected in code words. In some embodiments, the memory device may complete the ECS procedure over multiple refresh commands, namely by performing a read (or read/modify) portion of the ECS procedure while a first refresh command is executed, and by performing a write portion of the ECS procedure while a second refresh command is executed. The ECS procedure described herein may facilitate avoiding signaling conflicts or interferences that may occur between the ECS procedure and other memory operations.

Abstract: Provided herein may be a memory controller and an operating method thereof. The memory controller may include: a read fail control circuit configured to perform, when the read operation fails, an assist read operation of determining optimal read voltages to be used to read the selected memory cells, and determine whether a threshold voltage distribution of the selected memory cells is an abnormal distribution based on read-related information obtained by the read operation and the assist read operation; and an error correction code (ECC) engine configured to perform an ECC decoding operation on hard decision data obtained by reading the selected memory cells using the optimal read voltages based on whether the threshold voltage distribution of the selected memory cells is the abnormal distribution.

Abstract: It is assumed that at least one of the plurality of nonvolatile semiconductor memory devices is a nonvolatile semiconductor memory device (hereinafter, referred to as a first memory device) in a low power consumption state in which error check processing and refresh processing cannot be performed. A storage apparatus releases a low power consumption state of a first memory device at a timing according to a lapsed time after the first memory device is in the low power consumption state and an estimated ambient temperature of the first memory device at the lapsed time. When the low power consumption state is released, the first memory device executes the error check processing and the refresh processing.

Abstract: Data storage method, apparatus, and system are disclosed. The data storage method includes: encoding a data block using an erasure coding to obtain corresponding multiple data fragments; separately writing the multiple data fragments to corresponding allocated storage nodes; and determining that writing of the data block is successful if a number of storage nodes to which data fragments is successfully written within a first defined time duration is greater than or equal to a defined value, wherein the defined value is greater than or equal to a number of data block fragments in the multiple data fragments and is less than or equal to a number of the multiple data fragments. As such, the latency of a data write can be reduced, and the performance stability can be improved when a storage node encounters a failure.

Abstract: Memory controllers, devices, modules, systems and associated methods are disclosed. In one embodiment, a memory module includes a pin interface for coupling to a bus. The bus has a first width. The module includes at least one storage class memory (SCM) component and at least one DRAM component. The memory module operates in a first mode that utilizes all of the first width, and in a second mode that utilizes less than all of the first width.

Abstract: A distributed storage network (DSN) stores sets of encoded data slices in sets of storage units. A first storage unit assigned to store an encoded data slice included in a set of encoded data slices transmits a rebuild request associated with the storage error to a second storage unit. The second storage unit generates the rebuilt encoded data slice in response to the rebuild request, and transmits the rebuilt encoded data slice back to the first storage unit, which stores the rebuilt encoded data slice.

Abstract: Techniques for Implementation of keeping data integrity in multiple dimensions are described. A single but relatively complicated engine is used to encode a line of original data bits in one dimension once and for all, while a linear array of simple engines are used in another dimension to keep revising sets of redundant data bits for successive lines of original data bits, where the redundant data bits become final when a last line of original data bits is accessed.

Abstract: A memory system includes a nonvolatile memory and a memory controller. The nonvolatile memory has data encoded with an error correction code stored therein. The memory controller reads data from the nonvolatile memory, calculates likelihood information from the read data and an LLR table for calculating the likelihood information, determines a parameter for a decoding process of the read data based on the likelihood information, executes the decoding process based on the determined parameter, and outputs a decoding result obtained by the decoding process.

Abstract: A memory system includes a non-volatile memory and a controller that includes a toggle encoder configured to encode first data having a first bit length and a first number of toggles, into second data having a second bit length longer than the first bit length and a second number of toggles smaller than the first number of toggles, and transmit the second data to the non-volatile memory. The memory system may further include a toggle decoder configured to decode third data received from the non-volatile memory into fourth data, the third data having the second bit length and the second number of toggles and the fourth data having the first bit length and the first number of toggles.

Abstract: A storage device includes a non-volatile memory including a plurality of memory blocks and a storage controller configured to control a read operation of the non-volatile memory. The storage controller receives power-off time information indicating a power-off time point at which the storage device is powered off, and power-on time information indicating a power-on time point at which the storage device is powered on, when the storage device is switched from a power-off state to a power-on state. The storage controller stores a power-off time stamp corresponding to the power-off time point and a power-on time stamp corresponding to the power-on time point in the non-volatile memory.