Abstract: In one implementation, a method comprises storing verification data and erasure codes separately in a plurality of storage devices. The method further comprises determining, by a processing device, whether data to be written to the plurality of storage devices is lost or corrupted using the verification data and the erasure codes.

Abstract: A RAID proxy storage-device-assisted data update system includes a RAID parity data storage device and a first RAID primary data storage device without storage-device-assisted data update functionality, and a second RAID primary data storage device with storage-device-assisted data update functionality. The second RAID primary data storage device receives a command that identifies updated primary data for the first RAID primary data storage device and, in response, retrieves the updated primary data, current primary data from the first RAID primary data storage device, and current parity data from the RAID primary parity data storage device. The second RAID primary data storage device performs an XOR operation using the updated primary data, the current primary data, and the current parity data to generate updated parity data, transmits the updated primary data to the first RAID primary data storage device, and transmits the updated parity data to the RAID parity data storage device.

Abstract: Aspects of the invention include using a cyclic redundancy code (CRC) multiple-input signature register (MISR) for early warning and fail detection. Received bits are monitored at a receiver for transmission errors. The monitoring includes receiving frames of bits that are a subset of frames of bits used by the transmitter to generate a multi-frame CRC. At least one of the received frames of bits includes payload bits and a source single check bit not included in the multi-frame CRC. It is determined whether a transmission error has occurred in the received frames of bits. The determining includes generating a calculated single check bit based at least in part on bits in the received frames of bits, and comparing the received source single check bit to the calculated single check bit. An error indication is transmitted to the transmitter if they don't match.

Abstract: An example apparatus to monitor memory includes an error manager to compare a first memory location of a first error in the memory to a plurality of memory locations in an error history log, the plurality of memory locations previously identified in the error history log based on errors detected in the memory locations, ones of the memory locations associated with corresponding counters that track the errors detected in the memory locations, and update a first one of the counters corresponding to the first memory location when a first address of the first memory location matches a second address of one of the memory locations in the error history log. The example apparatus further includes a command generator to transmit a command to an error corrector to perform error correction on the first memory location when the first one of the counters satisfies a threshold.

Abstract: An error correction circuit using a BCH code may include a decoder performing at least one of a first error correction decoding using a first error correction capability or a second error correction decoding using a second error correction capability and an encoder generating a codeword based on a message and a generation matrix corresponding to the first error correction capability and generating an additional parity based on the codeword and one or more rows of a parity check matrix corresponding to the second error correction capability, wherein a syndrome vector generated based on a read vector corresponding to the codeword is used during the first error correction decoding and an additional syndrome generated based on the additional parity is used during the second error correction decoding, and wherein the one or more rows are extended from a parity check matrix corresponding to the first error correction capability.

Abstract: The present invention provides channel interleaving method of a polar (Polar) code. The method includes: determining an M_r-row and M_c-column matrix used for interleaving, and permutating, based on permutation patterns of the column sequence numbers and/or permutation patterns of the row sequence numbers, the matrix into which the to-be-interleaved bits are written. The permutation patterns of the column sequence numbers are represented by: [Pc(0), Pc(1), . . . , Pc(ic), . . . , Pc(M_c?1)]. Pc(ic) is obtained by performing pruned bit reverse (PBR, pruned bit reverse)-based mapping on the column sequence number ic. The permutation patterns of the row sequence numbers are represented by: [Pr(0), Pr(1), . . . , Pr(ir), . . . , Pr(M_r?1)]. Pr(ir) is obtained by performing pruned bit reverse (PBR, pruned bit reverse)-based mapping on the row sequence number ir; and reading interleaved bits from the permutated matrix.

Abstract: Disclosed in some examples are methods, systems, devices, and machine-readable mediums which optimize one or more metrics of a communication system by intentionally changing symbols in a bitstream after encoding by an error correction coder, but prior to transmission. The symbols may be changed to meet a communication metric optimization goal, such as decreasing a high PAPR, reducing an error rate, reducing an average power level (to save battery), or altering some other communication metric. The symbol that is intentionally changed is then detected by the receiver as an error and corrected by the receiver utilizing the error correction coding.

Abstract: The present disclosure relates to a circuit testing system, including a control circuit and an I/O interface circuit. The control circuit is electrically connected to a test machine, and is configured to receive a scan control signal. The I/O interface circuit is electrically connected to the control circuit, the test machine, the scan chain circuit and a circuit under test. When the scan control signal is at a first level, the control circuit is configured to control the I/O interface circuit to propagate a scan test signal sended from the test machine to the scan chain circuit. When the scan control signal is at a second level, the control circuit is configured to control the I/O interface circuit to propagate a response signal generated by the circuit under test to the test machine.

Abstract: Systems and methods presented herein provide for increasing a contention window of a UE employing a LTE communications operating in a radio frequency (RF) band comprising a conflicting wireless technology. In one embodiment, an eNodeB receives a transport block of data from a user equipment (UE). The transport block includes a cyclic redundancy check (CRC). The eNodeB then determines a checksum of the transport block based on the CRC, fails the checksum, and transmits a non-acknowledgement (NACK) of the transport block to the UE based on the failed checksum. The UE, in response to the NACK, increases a contention window and re-transmits the transport block to the eNodeB.

Abstract: A method for execution by a computing device of a storage network begins by obtaining a credential to be added to a local authentication list, where the credential authenticates, during a first time period, at least one of an access request and a requesting device, and where the local authentication list is stored in temporary memory of the computing device and is stored as a plurality of sets of encoded authentication slices in a set of storage units. The method continues by updating the local authentication list stored in the temporary memory to include a representation of the credential. The method continues by encoding the representation to produce a set of encoded authentication slices, where a decode threshold number of encoded authentication slices is needed to recover the representation. The method continues by sending the set of encoded authentication slices to the set of storage units for storage therein.

Abstract: A system and a method are disclosed for error correction during operations of a memory system. For example, during a read operation, the error correction includes a read retry determination to account for link errors that are detectable by cyclic redundancy check (CRC) but not correctable by error correction coding (ECC). Reducing the number of read retry operations performed may improve system performance by reducing the number of clock cycles spent on retry operations that could have otherwise been allocated for other system services (e.g., completing read and write operations). Additional CRC calculations and checks may be used to determine when to perform a retry in addition to existing CRC and ECC checks, reducing the number of potential retry operations and improving system performance.

Abstract: An encoding method and apparatus are provided. The method by a transmit end includes: performing check encoding on to-be-encoded information to obtain a check encoding codeword that comprises K information bits and J check bits; performing an interleaving operation on the check encoding codeword with an interleaving sequence including J subsequences, and an ith subsequence includes a position index of an element 1 in an intermediate result vector Ti and a value of (K+i), where 1?i?J, i is an integer, Ti=(˜M)&(Vi), M=M|(Vi), M is a masked vector, Vi is a column vector of a checking part matrix P, P is a submatrix of a generator matrix G for check encoding, ˜ represents a bit-by-bit NOT operation, & represents a bit-by-bit AND operation, and | represents a bit-by-bit OR operation; and performing polar encoding on a check encoding codeword obtained after the interleaving operation.

Abstract: In some examples, a polar decoder for implementing polar decoding of a codeword can be configured to implement alogarithmic likelihood ratio (LLR), an even bit, and an odd bit buffer, respectively. The polar decoder can be configured to employ a list-to-buffer mapping state register for the LLR buffer for loading LLR values for each path at a given stage of a decoding graph. The polar decoder can be configured to update and store LLR values for each path at the given stage. The polar decoder can be configured to employ a list-to-buffer mapping state register for the even bit buffer for loading even bit values from the even bit buffer and loading odd bit values from the odd bit buffer, and updating even or odd bit values for each path at the given stage of the decoding graph.

Abstract: The code block segmentation method includes: a base station determining whether to use the maximum length of a first pre-set information bit for code block segmentation or to use the maximum length of a second pre-set information bit for code block segmentation; if it is determined to use the maximum length of the first pre-set information bit for code block segmentation, the base station segmenting a transport block into one or more segments by taking the maximum length of the first pre-set information bit as an upper limit; and if it is determined to use the maximum length of the second pre-set information bit for code block segmentation, the base station segmenting a transport block into one or more segments by taking the maximum length of the second pre-set information bit as an upper limit, wherein the maximum length of the first pre-set information bit is greater than the maximum length of the second pre-set information bit.

Abstract: Disclosed are devices, systems and methods for improving performance of a block of a memory device. In an example, performance is improved by implementing soft chipkill recovery to mitigate bitline failures in data storage devices. An exemplary method includes encoding each horizontal row of cells of a plurality of memory cells of a memory block to generate each of a plurality of codewords, and generating a plurality of parity symbols, each of the plurality of parity symbols based on diagonally positioned symbols spanning the plurality of codewords.

Abstract: Application data and error correction code (ECC) checkbits associated with that application data are stored in a first memory. The ECC checkbits, but not the application data, are stored in a second memory. In response to a request to read the application data from the first memory, the ECC checkbits from the first memory are also read and used to detect, and possibly correct, errors in the read application data. The ECC checkbits are further output from both the first and second memories for bit-by-bit comparison. In response to a failure of the bit-by-bit comparison, a signal indicating possible malfunction of one or the other or both of the first and second memories is generated.

Abstract: Some embodiments are directed to a test apparatus for testing a device. The apparatus includes a test device having a memory for storing data processing instructions and processors configured, when the data processing instructions are executed, to execute test code in order to implement a test operation on the device being tested. The test code defines test patterns and test algorithms to be applied to instruments for testing the device being tested, and is in a first format that is independent of the test interface between the test device and the device being tested. The apparatus also includes an interface controller coupled to the device being tested and configured to convert communications generated by the test device during the execution of the test code into a second format suitable for the test interface, and to convert communications from the device being tested into the first format.

Abstract: Examples described herein relate generally to content aware bit flipping decoders. An example device includes a decoder. The decoder is configured to: process one or more flip thresholds based on statistics of data to be decoded; and perform a bit flipping algorithm on the data using the one or more processed flip thresholds. Other examples relate to methods of processing one or more flip thresholds based on statistics of data to be decoded and performing a bit flipping algorithm on the data using the one or more processed flip thresholds.

Abstract: Disclosed are devices, systems and methods for improving a quality of service of an adaptive soft decoder in a non-volatile memory device. An example method includes selecting, based on current operating conditions of the non-volatile memory device, a first decoder parameter set from an ordered plurality of decoder parameter sets, each decoder parameter set corresponding to a distinct operating condition of the non-volatile memory device and comprising parameters related to a soft decoding operation; performing, based on the first decoder parameter set, the soft decoding operation; upon a determination that the soft decoding operation has succeeded, reordering the ordered plurality of decoder parameter sets to place the first decoder parameter set at a start of the ordered plurality of decoder parameter sets, and otherwise, performing the soft decoding operation based on a second decoder parameter set selected from the ordered plurality of decoder parameter sets.

Abstract: A system and method for virtually addressing an array of accelerator tiles of a mixed-signal integrated circuit includes testing each of a plurality of distinct matrix multiply accelerator (MMA) tiles of a grid of MMA tiles, the grid of MMA tiles being defined by the plurality of distinct grid of MMA tiles being arranged in a plurality of rows and a plurality of columns along an integrated circuit, each of the plurality of distinct MMA tiles within the grid of MMA tiles having a distinct physical address on the integrated circuit; identifying one or more defective MMA tiles within the grid of MMA tiles based on the testing; and configuring the grid of MMA tiles with a plurality of virtual addresses for routing data to or routing data from one or more non-defective MMA tiles of grid of MMA tiles based on identifying the one or more defective MMA tiles.