Abstract: A memory system includes a plurality of memory devices, a buffer memory, and a controller. The controller generates bitmap information for a plurality of pages to distinguish a first page on which a read operation has succeeded from a second page on which the read operation has failed, and stores the bitmap information in the buffer memory, whenever completing the read operation for each of the plurality of pages. The controller generates parity data by cumulatively performing a parity operation on data of the first page whenever performing the read operation on each of the plurality of pages, and stores the parity data in the buffer memory. The controller checks the bitmap information after the read operations on the plurality of pages are completed, and recovers data of the second page by referring to the parity data when the second page is present among the plurality of pages.

Abstract: Devices, systems, and methods for dynamic control of a quasi-cyclic low-density parity-check (QC-LDPC) bit-flipping decoder are described. An example method includes receiving a noisy codeword based on a transmitted codeword generated from an irregular QC-LDPC code, performing a plurality of decoding iterations on the received noisy codeword, each of the plurality of decoding iterations comprising processing of N circulant matrices, performing, before processing a current circulant matrix in a current M-th iteration of the plurality of decoding iterations, operations that include computing a number of bit flips that have occurred over the processing of N previous circulant matrices, the N previous circulant matrices spanning the current M-th iteration and an (M?1)-th iteration, wherein M and N are positive integers, and wherein M?2, and updating, based on the number of bit flips, a bit-flipping threshold, and processing, based on the updated bit-flipping threshold, the current circulant matrix.

Abstract: An LDPC decoding method of a received signal including a plurality of received symbols is provided. A decoding apparatus selects a perturbation space in which perturbation is to be performed based on a code length of the received signal and a maximum number of perturbation rounds indicating a number of perturbation rounds that can be performed, and performs a perturbation round. The decoding apparatus performs perturbation on a corresponding received symbol among the plurality of received symbols in each perturbation round, and decodes the received signal on which the perturbation has been performed. The decoding apparatus determines that decoding is successful when there is a perturbation round in which a decoding result of the received signal satisfies a predetermined condition.

Abstract: A data storage device includes a nonvolatile memory device configured to read and output a plurality of data chunks; and a data processing block configured to perform decoding on the data chunks, the data processing block comprising a sequencer configured to generate a decoding information on the data chunks; and a core circuit configured to perform normal decoding on a first data chunk among the data chunks based on the decoding information, and perform fast decoding on a second data chunk among the data chunks depending on whether a result of the normal decoding satisfies a fast decoding condition, wherein the fast decoding requires a shorter execution time than the normal decoding.

Abstract: A data processing system includes a storage medium, and a controller including a data processing block, configured to receive data from a host, transmit the received data to the storage medium, read data from the storage medium in response to a read request from the host, and decode the read data by the data processing block according to multiple decoding modes. The data processing block includes a first decoder and a second decoder, and is configured to manage the first decoder and the second decoder to run the decoding for the read data, and activate a fast decoding having shorter latency than a normal decoding after a fast decoding condition is satisfied.

Abstract: A decoding method and apparatus are provided, to improve a degree of parallelism in decoded bit decisions and reduce a decoding delay. The method includes: performing a hard decision on each LLR in an inputted LLR vector having a length of M to obtain a first vector, where M?N and N is a length of to-be-decoded information; sequentially performing negation of some elements of the first vector to obtain L vectors; and then determining decoding results of the LLR vector based on the L vectors.

Abstract: Certain aspects of the present disclosure generally relate to wireless communications and, more particularly, to methods and apparatus for dynamic frozen polar codes, for example, for control channels. An exemplary method may be performed at the encoder. The method generally includes encoding a stream of bits using a polar code. The encoding includes selecting a first set of channel indices for encoding information bits. The encoding includes selecting a second set of the channel indices smaller than a channel index for a first information bit for encoding fixed frozen bits. The encoding includes selecting remaining channel indices for dynamic frozen (PCF) bits having values based on one or more of the information bits. The method includes transmitting the encoded stream of bits.

Abstract: Apparatuses, systems, and methods for error correction. A memory device may have a number of memory cells each of which stores a bit of information. One or more error correction code (ECC) may be used to determine if the bits of information contain any errors. To mitigate the effects of failures of adjacent memory cells, the information may be divided into a first group and a second group, where each group contains information from memory cells which are non-adjacent to other memory cells of that group. Each group of information may include data bits and parity bits used to correct those data bits. For example, as part of a read operation, a first ECC circuit may receive information from even numbered memory cells, while a second ECC circuit may receive information from odd numbered memory cells.

Abstract: There is provided a method of sequential list decoding of an error correction code (ECC) utilizing a decoder comprising a plurality of processors. The method comprises: a) obtaining an ordered sequence of constituent codes usable for the sequential decoding of the ECC; b) executing, by a first processor, a task of decoding a first constituent code, the executing comprising: a. generating decoding candidate words (DCWs) usable to be selected for decoding a subsequent constituent code, each DCW associated with a ranking; b. for the first constituent code, upon occurrence of a sufficiency criterion, and prior to completion of the generating all DCWs and rankings, selecting, in accordance with a selection criterion, at least one DCW; c) executing, by a second processor, a task of decoding a subsequent constituent code, the executing comprising processing data derived from the selected DCWs to generate data usable for decoding a next subsequent constituent code.

Abstract: A memory system according to an embodiment includes a nonvolatile memory and a memory controller. The memory controller converts a received value read from the nonvolatile memory into first likelihood information by using a first conversion table, executes decoding on the first likelihood information and outputting a posterior value, outputs an estimated value of the received value obtained on the basis of the posterior value in a case where the decoding is successful. The memory controller generates a second conversion table on the basis of the posterior value in a case where the decoding fails. The memory controller converts the received value into second likelihood information by using the second conversion table in a case where the second conversion table has been generated, and executes decoding on the second likelihood information and outputs a posterior value.

Abstract: According to some embodiments, a method of operation of a wireless transmitter in a wireless communication network comprises: encoding a set of information carrying data bits u of length K with a linear outer code to generate a set of outer parity bits p along with the data bits u; interleaving the set of outer parity bits p and the data bits u using a predetermined interleaving mapping function that depends on the number of data bits K and is operable to distribute some bits of the set of parity bits p in front of some data bits u; and encoding the interleaved bits using a Polar encoder to generate a set of encoded bits x. Various interleaving mapping functions are disclosed.

Abstract: [Problem] Encoding and decoding techniques capable of speeding up an error-correction decoding process utilizing channel polarization are provided. [Solution] In an encoding device, the information bit sequence is input on division for each designated bit length; error-correction encoding is performed on an information block of the designated bit length to generate L M-bit codes, each M-bit code having a predetermined bit length M; the L M-bit codes are converted into M L-bit blocks each having a predetermined bit length of L; the M L-bit blocks are Polar-converted to M L-bit codes, each L-bit code having a bit length of L, through channel polarization processing; and division of the information bit sequence is determined based on channel polarization information.

Abstract: In certain aspects, a method for sending data over a bus comprises: calculating a parity check code for a new data code, wherein the new data code comprises a number of bits in the new data code; calculating a Hamming distance between the new data code and a prior data code; and if the Hamming distance is greater than half of the number of bits in the new data code: inverting the new data code and the parity check code to obtain an inverted new data code and an inverted parity check code; and sending the inverted new data code and the inverted parity check code to the bus.

Abstract: The present disclosure relates to a pre-5th-Generation (5G) or 5G communication system to be provided for supporting higher data rates Beyond 4th-Generation (4G) communication system such as Long Term Evolution (LTE). A method of decoding a signal in a communication system includes receiving an encoded bit-stream corresponding to message bits and first Cyclic Redundancy Check (CRC) bits, obtaining a codeword through a traceback for at least part of the encoded bit-stream, generating second CRC bits by performing CRC encoding on the codeword, and performing decoding based on at least part of the second CRC bits.

Abstract: Methods and apparatuses for HARQ in a non-terrestrial network are disclosed. An operation method of a first node may comprise receiving a transport block (TB) from a second node; classifying total soft bits for the TB into information values and sign values; configuring the information values of the total soft bits into one or more subsets; performing a compression operation on each of the one or more subsets; and performing a compression operation on the sign values. Therefore, performance of the communication system can be improved.

Abstract: The system receives, by a first controller, data to be written to a first storage device. The data may not be accompanied by a cyclic redundancy check (CRC) signature. The system calculates, by the first controller, a first error detection code based on the data, and writes the data and the first error detection code to the first storage device. The system calculates a second error detection code based on the written data. The system performs a first integrity check of the written data by determining whether the second error detection code matches the first error detection code. The system performs a second integrity check of the written data by: obtaining one or more additional error detection codes from one or more other storage devices, wherein an obtained error detection code is calculated by a controller of a corresponding storage device; and determining whether the first error detection code matches the one or more additional error detection codes.

Abstract: A method of controlling verification operations for error correction of a non-volatile memory device includes the following. A tolerated error bit (TEB) number for error correction of the non-volatile memory device is set to a first value to control verification operations in accordance with the TEB number. After at least one portion of the non-volatile memory device is programmed for a specific number of times, the TEB number is changed from the first value to a second value to control the verification operations in accordance with the TEB number, wherein the second value is greater than the first value and is less than or equal to the TEB threshold. The method may be performed while the at least one portion of the non-volatile memory device is programmed and verified.

Abstract: A memory system includes a Reed-Solomon (RS) decoder, a reliability tracking circuit, and an erasure control circuit. The RS decoder performs an error correction decoding operation of ‘K’-number of symbols outputted from a memory medium. The reliability tracking circuit generates and stores information on a reliability of the symbols, error occurrence possibilities of which are distinguished into a plurality of different levels according to the error correction decoding operation performed by the RS decoder. The erasure control circuit controls the RS decoder such that the symbols are erased in order of the reliability of the symbols from a low reliable symbol to a high reliable symbol and the error correction decoding operation is performed according to the information on the reliability of the symbols stored in the reliability tracking circuit.

Abstract: Provided herein may be a controller, a memory system including the controller, and a method of operating the memory system. The controller may include a processor configured to control a read operation of a memory device in response to a read command received from a host and an error correction circuit configured to perform an error correction operation on read data received from the memory device during the read operation. The processor may determine deterioration characteristics of the memory device during the read operation, and control the memory device to select and perform any one of a re-program operation and a reclaim operation on memory cells on which the read operation has been performed.

Abstract: Embodiments of polar encoding/decoding methods and apparatuses are described. CRC encoding is performed on an information block to obtain a CRC encoded block with a length of B, where a CRC length is Lcrc, an information block length is K, and B=K+Lcrc. The CRC encoded block is interleaved. Lpc CRC bits in the interleaved encoded block are located between bits of the information block. Each CRC bit of the Lpc CRC bits is located after all bits checked by using the CRC bit. Lpc is an integer greater than 0 and less than Lcrc. The interleaved encoded block is mapped to information bits. A frozen bit is set to an agreed fixed value. Polar encoding is performed on the information bits and the frozen bit to obtain a polar encoded codeword to improve performance of a CA-polar code.