Abstract: A method, system and computer program product are disclosed for using a Field Programmable Gate Array (FPGA) to simulate operations of a device under test (DUT). The DUT includes a device memory having a number of input ports, and the FPGA is associated with a target memory having a second number of input ports, the second number being less than the first number. In one embodiment, a given set of inputs is applied to the device memory at a frequency Fd and in a defined cycle of time, and the given set of inputs is applied to the target memory at a frequency Ft. Ft is greater than Fd and cycle accuracy is maintained between the device memory and the target memory. In an embodiment, a cycle accurate model of the DUT memory is created by separating the DUT memory interface protocol from the target memory storage array.

Abstract: In one embodiment, the present invention includes a method for receiving incoming data in a processor and performing a checksum operation on the incoming data in the processor pursuant to a user-level instruction for the checksum operation. For example, a cyclic redundancy checksum may be computed in the processor itself responsive to the user-level instruction. Other embodiments are described and claimed.

Abstract: A method for channel encoding in a communication or broadcasting system is provided. The method includes determining a block size Z, and performing encoding based on the block size and a first matrix corresponding to the block size, wherein the first matrix is determined based on information and a plurality of second matrices, and wherein a part of a column index indicating a position of a non-zero element in each row of the information includes an index according to mathematical expression 22 above.

Abstract: Disclosed herein are techniques to provide forward error correction for a high-speed interconnect symbol stream, such as, DisplayPort. The symbol stream may be split into FEC blocks and parity bits generated for each of the FEC blocks. The parity bits may be interleaved, encoded, and transmitted over an interconnect along with the symbol stream to provide forward error correction for the symbol stream.

Abstract: Disclosed are devices, systems and methods improving the convergence of a soft bit-flipping decoder in a non-volatile memory device. An example method includes receiving a noisy codeword, the codeword having been generated based on a parity check matrix of an LDPC code and provided to a communication channel prior to reception by the soft bit-flipping decoder, generating, based on the noisy codeword, one or more messages for passing between a plurality of variable nodes and a plurality of check nodes of the soft bit-flipping decoder, generating a reliability metric for each of the one or more messages, storing the reliability metric only for messages comprising magnitudes that are less than or equal to a predetermined threshold value; and performing, based on the one or more messages and the associated reliability metric for at least one of the one more messages, a single decoding iteration of the soft bit-flipping decoder.

Abstract: A method includes receiving a time domain resource allocation (TDRA) list configuration including entries, each including a resource allocation that includes a slot offset value. L1 signaling is received indicating a minimum slot offset value. Downlink control information (DCI) is decoded on a physical downlink control channel in a slot. An index is obtained from the decoded DCI, identifying an entry in the TDRA list. A particular slot offset value identified by the index is retrieved from the TDRA list and compared with the minimum slot offset value. If the particular slot offset value is less than the minimum slot offset value, the entry is invalid. If the particular slot offset value is greater than or equal to the minimum slot offset value, a physical downlink shared channel is received.

Abstract: Information reduction in data processing environments includes at least one of: one or more Error Correcting Codes that decode n-vectors into k-vectors and utilize said decoding to information-reduce data from a higher dimensional space into a lower dimensional space. The information reduction further provides for a hierarchy of information reduction allowing a variety of information reductions. Transformations are provided to utilize available data space, and data may be transformed using several techniques including windowing functions, filters in the time and frequency domains, or any numeric processing on the data.

Abstract: Systems and methods are described for modifying input and output (I/O) to an object storage service by implementing one or more owner-specified functions to I/O requests. A function can implement a data manipulation, such as filtering out sensitive data before reading or writing the data. The functions can be applied prior to implementing a request method (e.g., GET or PUT) specified within the I/O request, such that the data to which the method is applied my not match the object specified within the request. For example, a user may request to obtain (e.g., GET) a data set. The data set may be passed to a function that filters sensitive data to the data set, and the GET request method may then be applied to the output of the function. In this manner, owners of objects on an object storage service are provided with greater control of objects stored or retrieved from the service.

Abstract: According to some embodiments, a method in a wireless transmitter comprises: receiving a plurality of bits for a wireless transmission; determining a maximum code block size for the transmission based on code rate, maximum code word size Nmax, and design parameters of the channel code; segmenting the plurality of bits into one or more code block segments such that no one of the one or more code block segments is larger than the determined maximum code block size; and transmitting the one or more code block segments to a wireless receiver. In particular embodiments, the design parameters of the channel code limit the maximum code block size to Kmax for any code rate. The determined maximum code block size may be limited by code rate and Nmax such that the maximum code block size does not exceed code rate times Nmax.

Abstract: This application provides a data processing method, a data processing apparatus, and a communications device. The data processing method includes: coding a first bit sequence, to obtain a second bit sequence, where the first bit sequence includes a first information bit and a first padding bit, and the second bit sequence includes a second information bit and a redundant bit; and storing the second bit sequence in a circular buffer.

Abstract: Techniques are described for improving the decoding latency and throughput of an error correction system that includes multiple decoders. For example, the error correction system intelligently distributes and balances the decoding of codewords between the different decoders. In particular, the error correction system can consider different factors associated with decoding various codewords including, for instance, the checksum of a codeword that is to be decoded, an estimated number of decoding iterations to decode the codeword by a decoder based on the checksum, and/or an accumulated number of decoding iterations for decoding by the decoder of the codeword in addition to other codewords already buffered for the decoder. Given these factors, the error correction system can generate a decision to decode the codeword by the decoder or by another decoder of the error correction system, where the decision optimizes the performance.

Abstract: According to certain embodiments, a method is provided for generating soft information for code bits of polar codes. The method includes receiving, by a decoder of a receiver, soft information associated with coded bits from a first module of the receiver and using a tree structure of the polar code to generate updated soft information. The updated soft information is output by the decoder for use by a second module of the receiver.

Abstract: A storage device sharing a host memory of a host, the storage device includes a serial interface that exchanges data with the host, and a storage controller that stores buffering data in a host memory buffer allocated by the host through the serial interface. The storage controller performs error correction encoding and error correction decoding on the buffering data.

Abstract: The present disclosure relates to methods and apparatus for testing the true capabilities of devices connected to a computer. Methods consistent with the present disclosure may include generating test commands to send to a data storage device under test while storing information related to the commands sent to the data storage device in a low latency buffer. The low latency buffer may temporarily store command related data while data from a plurality of commands are organized and persistently stored in memory of a persistent data storage device. The low latency buffer may include or be comprised of high speed random access memory and the persistent data storage device may be a solid state drive or hard disk drive. Preferably, the persistent data storage device will store command test sequences that span long periods of time of hours or days.

Abstract: A controller includes an interface and circuitry. The interface is coupled to multiple memory cells. The circuitry stores a code word in a group of the memory cells, reads the code word using different thresholds to produce first and second readouts, and checks whether approximating each of first and second numbers of readout errors based on syndrome weights is valid. In response to determining that only the approximation of the second number of errors is valid, the circuitry produces a combined readout by replacing a portion of the bits in the second readout with corresponding bits of the first readout, calculates an enhanced syndrome weight for the combined readout and estimates the first number of errors based on the enhanced syndrome weight. The circuitry improves readout performance from at least the group of the memory cells using at least one of the estimated first and second numbers of errors.

Abstract: A non-limiting example includes data storage circuitry. The data storage circuitry includes a built-in self-test (BIST) engine. The data storage circuitry includes a memory array including memory cells. The memory array is configured to store data based on a read-write vector associated with an address vector that includes memory addresses and according to a bit-write vector that defines bit-write enablement for the memory addresses. The memory array is configured to output a stored data vector. The data storage circuitry includes a selector configured to receive the bit-write vector, and to output a selected vector based on an initialization vector and a comparison vector based at least in part on the bit-write vector. The data storage circuitry includes a comparator configured to receive the stored data vector and the selected vector, and to output an error based on discrepancies between the stored data vector and the selected vector.

Abstract: This application provides an encoding method and apparatus in wireless communications between a network device and a terminal. The method includes: performing CRC encoding on A to-be-encoded information bits based on a CRC polynomial, to obtain a first bit sequence, where the first bit sequence includes L CRC bits and A information bits, L=6; and performing polar encoding on the first bit sequence. Based on an improved CRC polynomial, encoding satisfying an FAR requirement is implemented.

Abstract: A method for execution by a computing device of a dispersed storage network includes obtaining resource information for a subset of storage units of a storage unit pool. W available storage units of the storage unit pool are identified in response to receiving a store data request. W choose S combinations of selecting S number of storage units of the W available storage units are identified. A plurality of rating levels is calculated based on the resource information, where each of the plurality of rating levels are assigned to a corresponding combination of the W choose S combinations. One combination of the W choose S combinations is selected based on the plurality of rating levels. Storage of data of the store data request is facilitated utilizing the S number of storage units of the selected one combination.

Abstract: The disclosure relates to a method performed by a wireless device, for receiving system information from a network node of a wireless communication system. The system information is received in a synchronization signal (SS) block of an SS burst set comprising at least one SS block. The system information is multiplexed with information providing a time index indicating which SS block of the SS burst set that is being received. The method comprises receiving the information providing the time index, and receiving the system information, which comprises descrambling the system information using a scrambling sequence generated based on the information providing the time index. The method also comprises determining an accuracy of the information providing the time index, based on an error-detection code related to the received system information. The disclosure also relates to corresponding network node method and apparatus.

Abstract: A storage cluster is provided. The storage cluster includes a plurality of storage nodes, each of the plurality of storage nodes having nonvolatile solid-state memory and a plurality of operations queues coupled to the solid-state memory. The plurality of storage nodes is configured to distribute the user data and metadata throughout the plurality of storage nodes such that the plurality of storage nodes can access the user data with a failure of two of the plurality of storage nodes. Each of the plurality of storage nodes is configured to determine whether a read of 1 or more bits in the solid-state memory via a first path is within a latency budget. The plurality of storage nodes is configured to perform a read of user data or metadata via a second path, responsive to a determination that the read of the bit via the first path is not within the latency budget.