Abstract: Technologies disclosed herein provide one example of a system that includes processor circuitry to be communicatively coupled to a memory circuitry. The processor circuitry is to receive a memory access request corresponding to an application for access to an address range in a memory allocation of the memory circuitry and to locate a metadata region within the memory allocation. The processor circuitry is also to, in response to a determination that the address range includes at least a portion of the metadata region, obtain first metadata stored in the metadata region, use the first metadata to determine an alternate memory address in a relocation region, and read, at the alternate memory address, displaced data from the portion of the metadata region included in the address range of the memory allocation. The address range includes one or more bytes of an expected allocation region of the memory allocation.

Abstract: A method for hardware assisted data lookup in a storage unit is provided. The method includes formatting data in at least one of a plurality of data formats for storage in the storage unit. The method includes configuring a logic unit with one or more parameters associated with the plurality of data formats and identifying incoming data with the one or more parameters as an instruction for execution.

Abstract: Various embodiments set forth techniques for taking a snapshot of virtual memory of a virtual machine. One technique includes allocating, in a persistent memory, one or more blocks associated with a virtual memory; detecting a write request associated with a first portion of the virtual memory; in response to detecting the write request associated with the first portion, prioritizing the first portion; based on the prioritizing, copying the first portion into the one or more blocks in the persistent memory ahead of a second portion of the virtual memory; and after copying the first portion: applying the write request to the first portion; and copying the second portion into the one or more blocks in the persistent memory.

Abstract: A type of translation lookaside buffer (TLB) invalidation instruction is described which specifically targets a first type of TLB which stores combined stage-1-and-2 entries which depend on both stage 1 translation data and the stage 2 translation data, and which is configured to ignore a TLB invalidation command which invalidates based on a first set of one or more invalidation conditions including an address-based invalidation condition depending on matching of intermediate address. A second type of TLB other than the first type ignores the invalidation command triggered by the first type of TLB invalidation instruction. This approach helps to limit the performance impact of stage 2 invalidations in systems supporting a combined stage-1-and-2 TLB which cannot invalidate by intermediate address.

Abstract: Disclosed is a compressed memory management method for a computer system having one or more processors (P1-PN), compressible main memory, secondary memory and an operating system. The compressible main memory has a compressed memory space comprising an active part directly accessible to said one or more processors (P1-PN), as well as an inactive part not directly accessible to said one or more processors (P1-PN) in the form of memory freed up by memory compression.

Abstract: Aspects relate to Input/Output (IO) Memory Management Units (MMUs) that include hardware structures for implementing virtualization. Some implementations allow guests to setup and maintain device IO tables within memory regions to which those guests have been given permissions by a hypervisor. Some implementations provide hardware page table walking capability within the IOMMU, while other implementations provide static tables. Such static tables may be maintained by a hypervisor on behalf of guests. Some implementations reduce a frequency of interrupts or invocation of hypervisor by allowing transactions to be setup by guests without hypervisor involvement within their assigned device IO regions. Devices may communicate with IOMMU to setup the requested memory transaction, and completion thereof may be signaled to the guest without hypervisor involvement. Various other aspects will be evident from the disclosure.

Abstract: A control table (22) defines information for controlling a processing component (20) to perform an operation. The table (22) comprises entries each corresponding to a variable size region defined by a first limit address and one of a second limit address and size. A binary search procedure is provided for looking up the table, comprising a number of search window narrowing steps, each narrowing a current search window of candidate entries to a narrower search window comprising fewer entries, based on a comparison of a query address against the first limit address of a selected candidate entry of the current search window. The comparison is independent of the second limit address or size of the selected candidate entry. After the search window is narrowed to a single entry, the query address is compared with the second limit address or size of that single entry.

Abstract: An apparatus comprises at least one processing device. The at least one processing device is configured to identify at least one logical storage device that has a first service level objective and is exhibiting a deficiency in one or more performance metrics, to identify one or more additional logical storage devices each having a second service level objective lower than the first service level objective and not exhibiting a deficiency in the one or more performance metrics, to generate at least one false-positive signal specifying the one or more additional logical storage devices as each exhibiting a deficiency in the one or more performance metrics, and to provide the at least one false-positive signal to at least one host device. The at least one host device is configured to respond to the at least one false-positive signal by throttling input-output operations for the one or more additional logical storage devices.

Abstract: A control device includes a first controller, a second controller and a storage. The first controller performs safety control for a drive device. The second controller performs standard control for the drive device. The storage is accessible by both the first and second controllers and includes a first storage area and a second storage area. The first storage area stores data involved with the safety control, and the second storage area stores data involved with the standard control. The first controller accesses both the first storage area and the second storage area, and the second controller accesses the second storage area but is restricted from accessing the first storage area.

Abstract: Systems, methods, and apparatus related to data storage devices. In one approach, a string of storage devices are chained together and coupled to a host device for storing data. Each storage device may, for example, execute read, write, or erase commands received from the host device. Each storage device in the chain is a master to the next storage device in the chain, and each storage device is a slave to the previous storage device in the chain. In one example, the host device is a system-on-chip. The chain can manage itself and is seen as a single large storage space to the host device. The host device does not require knowledge about each individual storage device, and each storage device does not require knowledge about the other storage devices in the chain (other than whether the storage device is attached to another storage device on its master port).

Abstract: The present disclosure relates to a memory controller and a method of operating the memory controller. The memory controller controlling a memory device including a plurality of planes includes a central processing unit (CPU) generating a command corresponding to a request from a host, a command queue storing the command, counter logic assigning to the command, number information corresponding to an order in which the command is generated and flag information indicating a level at which an operation corresponding to the command is performed, and a command queue controller controlling the command queue to transfer the command stored in the command queue to one of the plurality of planes corresponding to the command on the basis of the number information and the flag information.

Abstract: A method and an apparatus of mapping table reconstruction based on a SSD, and a computer device are disclosed by the present application, and the method includes: acquiring the mapping table reconstruction request based on the SSD; scanning starting from the last physical page of the corresponding physical block according to the mapping table reconstruction request based on the SSD; reading the corresponding logical address and N logical address offsets from a data area of the current physical page, where N is the positive integer greater than 1; acquiring logical addresses corresponding to N adjacent pages in sequence according to the logical address corresponding to the current physical page and the N logical address offsets; reconstructing a mapping relationship between logical addresses and physical addresses according to the logical address corresponding to the current physical page and the logical addresses corresponding to the N adjacent pages.

Abstract: Systems and processes for efficient accessing, storing and transmitting of fixed data elements and dynamic data elements, each having its own native form. The data elements are organized according to a schema, with (a) all fixed data elements stored in their native forms in a fixed memory allocation, and (b) each dynamic data element stored in memory in its own native form, in its own data allocation. With this memory structure, computational overhead of converting data elements from their native forms to JSON, XML or other markup language is avoided, making accessing data (getting), updating data (setting), converting data to a serial stream for transmission or other manipulation (serializing), deserializing, and other manipulations of the data elements much more CPU efficient and requiring less bandwidth.

Abstract: A micro-threaded memory device. A plurality of storage banks are provided, each including a plurality of rows of storage cells and having an access restriction in that at least a minimum access time interval must transpire between successive accesses to a given row of the storage cells. Transfer control circuitry is provided to transfer a first amount of data between the plurality of storage banks and an external signal path in response to a first memory access request, the first amount of data being less than a product of the external signal path bandwidth and the minimum access time interval.

Abstract: Dynamically provisionable and allocatable memory external to a requesting apparatus may be provided. A request for primary memory may be made by an application executing on a client. An allocation logic unit may determine an allocation strategy in response to the request. As part of the allocation strategy, the allocation logic unit may identify memory appliances on which memory regions are to be allocated. The allocated memory regions may form the primary memory that is allocated to the requesting application. The allocation logic unit may send region allocation requests to region access unit of the respective memory appliances. The memory appliances on which the memory regions are allocated may be external to the client. The application may access the allocated memory regions via client-side access in which one or more processors in the client and/or the memory appliances are bypassed.

Abstract: Methods, systems, and apparatus, including computer programs encoded on computer storage media, for executing concurrent writes to a data store. One of the systems includes a data store comprising a plurality of storage segments, wherein each storage segment comprises a plurality of blocks; and an allocator system comprising: a plurality of threads, and a plurality of bitmaps each corresponding to a respective storage segment of the data store, wherein the allocator system is configured to perform operations comprising: assigning a respective bitmap to each thread of the plurality of threads; and executing, by each thread of the plurality of threads, one or more write requests to one or more blocks of the storage segment corresponding to the thread using the bitmap assigned to the thread, wherein executing a write request by a thread includes updating the bitmap assigned to the thread.

Abstract: A processing device of a memory sub-system can monitor a plurality of received commands to identify a forced unit access command. The processing device can identify a metadata area of the memory device based on the forced unit access command. The processing device can also perform an action responsive to identifying a subsequent forced unit access command to the metadata area.

Abstract: Apparatus and method for managing metadata in a data storage device such as a solid-state drive (SSD). The metadata are stored in combined (combo) pages in a non-volatile memory (NVM) each having first and second level map entries. The second level map entries provide a logical-to-physical address translation layer for user data blocks stored to the NVM, and the first level map entries describe the second level map entries in the combo page. A global map structure is accessed to identify a selected combo page in the NVM associated with a pending access command. The first and second level map entries are retrieved from the combo page, and the second level map entries are used to identify a target location for the transfer of user data blocks to or from the NVM.

Abstract: A method of operating a storage device includes receiving, at the storage device, a meta information transfer command based on a data read request. The meta information transfer command is received from a host device. The method further includes receiving, at the storage device, a data read command corresponding to the data read request and the meta information transfer command. The data read command is received from the host device. The method further includes receiving, at the storage device, a plurality of meta data corresponding to the data read request and the meta information transfer command. The plurality of meta data is received from the host device. The method further includes performing a data read operation, at the storage device, based on the data read command and the plurality of meta data.

Abstract: According to one embodiment, a memory system includes a nonvolatile memory and a controller which controls the nonvolatile memory. The controller notifies to an outside an extensive signal which indicates a predetermined state of the nonvolatile memory or the controller.