Abstract: Method providing resilient execution of a service on a computing device. The service is stored in a non-volatile memory of the computing device and comprises instructions executable by a processor of the computing device. The processor generates an operational instance of the service, which comprises a reference to the service. The processor stores the operational instance of the service in the non-volatile memory with a read-write access right. The processor launches an executable instance of the service associated to the operational instance of the service. The launching comprises copying the instructions of the service from the non-volatile memory to a volatile memory of the computing device. The launching further comprises executing the instructions of the service copied into the volatile memory. The processor adds data generated by the execution of the instructions of the service to the operational instance of the service for permanent storage in the non-volatile memory.

Abstract: A gate signal control circuit of a DDR memory system includes a comparing circuit, a flag generator and a signal generator. The comparing circuit receives a first data strobe signal and a second data strobe signal, and generates an internal data strobe signal. The flag generator receives a physical layer clock signal and a read enable signal, and generates plural flag signals. The signal generator receives the internal data strobe signal and the plural flag signal, and generates a gate signal. When plural read commands are issued, the flag generator sets the flag signals according to the physical layer clock signal and the read enable signal. When a read data is received, the signal generator opens the gate signal according to a preamble, and the signal generator samples the plural flag signals to determine the timing of closing the gate signal.

Abstract: A computer-implemented method is provided for generating a sequence of commands for replicating data on a source storage system to a destination storage system. The source and destination storage system support a first and a second remote file access protocol. The method involves i) scanning a directory of the source storage system for file system objects by the first and second remote file access protocol thereby obtaining a respective first and second representation of the file system objects; and ii) generating the sequence of commands based on the first and second representation and based on a predetermined rule set comprising rules for generating a command for replicating a file system object depending on a difference in representation of file system objects by the first and second remote file access protocol.

Abstract: Data processing method, apparatus, and mobile terminal are provided. A requesting end adds a reserved field to data to be stored to obtain target data, and sends the target data to a storing end. The storing end allocates a memory to cache the target data, generates data metadata of the data to be stored in the target data, and writes the data metadata to a memory location corresponding to the reserved field in the memory. The embodiments of the present disclosure realize zero copying, ensure the efficiency of data storage, and improve the system performance.

Abstract: A data mover selection system includes a memory system coupled to first and second data mover devices, and an operating system coupled to the first and second data mover devices. The operating system determines that a first data transfer operation provides for the transfer of data between first and second memory locations in the memory system, and identifies the first data mover device for performing the first data transfer operation based on the first data mover device having a higher priority relative to the second data mover device for performing data transfers between the first and second memory locations in the memory system. In response, the operating system transmits a first data transfer instruction to the first data mover device that causes the first data mover device to perform the first data transfer operation to transfer data between the first and second memory locations in the memory system.

Abstract: Improved scaling of an ordered event stream (OES) is disclosed. In contrast to conventional scaling of an OES that, in immediate response to loading exceeding a given processor performance level, merely divides a segment into segments having similar key space size, and then determines an alternate OES topology. The alternate OES topology can be selected from among ranked alternate OES topologies. The alternate OES topology can be implemented where the expected performance will meet a threshold level of improvement over an existing OES topology. Moreover, the alternate OES topology of the disclosed subject matter can comprise two or more two new segments that can have dissimilar key space sizes. Additionally, the two or more two new segments of the alternate OES topology can provide the same, or similar, loading relative to performance levels of corresponding processing instances, even where the performance levels of corresponding processing instances are also dissimilar.

Abstract: A system has a collection of central processing units. Each central processing unit is connected to at least one other central processing unit and has a path into flash memory resources. A central processing unit supports a mapping from a data address space, to a flash memory virtual address space, to a flash memory virtual page number to a flash memory physical address space.

Abstract: An integrated circuit (IC) can include a decomposer data mover circuit configured to read sub-arrays from array data stored in a source memory; generate metadata headers for the sub-arrays, wherein each metadata header includes location information indicating location of a corresponding sub-array within the array data; create data tiles, wherein each data tile includes a sub-array and a corresponding metadata header; and output the data tiles to compute circuitry within the IC. The IC can include a composer data mover circuit configured to receive processed versions of the data tiles from the compute circuitry; extract valid data regions from the processed versions of the data tiles; and write the valid data regions to a destination memory based on the location information from the metadata headers of the processed versions of the data tiles.

Abstract: Storing data volumes in virtual and physical address spaces such that the data units are contiguous in virtual address space but fragmented in physical address space. The mapping between virtual and physical address space is managed by a storage controller that is configured to implement deletes reversibly with a so-called soft delete, the soft delete being reversible up to a later permanent or hard delete. A soft delete triggers a compaction in which the data units of the to-be-deleted volume are gathered together in physical address space. During the time between compaction and hard delete (or restore), the soft deleted volume is thus stored in a space efficient manner. Moreover, the subsequent hard delete can be performed more quickly than if the soft deleted volume were still fragmented across physical address space freeing up space quicker.

Abstract: In a method for accessing a storage system, a client in the storage system identifies a logical address of a storage device, and queries a management server regarding a mapping between the storage device and a start address of a submission queue (SQ) in the memory of the storage node. The client then sends an access request including the logical address of the storage device directed to the start address of the SQ to a network interface card NIC of the storage node. The NIC receives and sends the access request to the start address of the SQ in the memory. The storage device obtains the access request from the start address of the SQ and executes the access request.

Abstract: Systems and methods for processing memory address spaces corresponding to a shared memory are disclosed. After a writer restart process, pre-restart writer pointers of a pre-restart writer addressable space in the shared memory are replaced with corresponding location independent pointers. A writer pointer translation table is rebuilt in the shared memory to replace an association of modified pre-restart writer pointers and pre-restart translation base pointers based on the pre-restart writer pointers, respectively, with an association of modified post-restart writer pointers and post-restart translation base pointers based on post-restart writer pointers, respectively. After the writer pointer translation table is rebuilt, the location independent pointers are replaced with post-restart writer pointers in the shared memory, respectively, and the post-restart writer pointers are stored in the shared memory for access by one or more readers of the shared memory.

Abstract: A memory system includes: a memory device including: a first memory block storing first map data, which maps a first logical address to a first physical address; and a second memory block storing first user data corresponding to the first map data; and a controller configured to: receive a warning signal from a host; and back up the first map data as second map data in response to the first logical address being provided along with a write command received after the warning signal is received; update the first map data to map the first logical address to a second physical address; suspend an erase operation being performed on the first user data is invalidated due to the write command; and restore the first map data based on the second map data and validate the invalidated first user data when it is determined that the host is infected by malware.

Abstract: A method of operating a storage device includes receiving, at the storage device, a meta information transfer command based on a data read request. The meta information transfer command is received from a host device. The method further includes receiving, at the storage device, a data read command corresponding to the data read request and the meta information transfer command. The data read command is received from the host device. The method further includes receiving, at the storage device, a plurality of meta data corresponding to the data read request and the meta information transfer command. The plurality of meta data is received from the host device. The method further includes performing a data read operation, at the storage device, based on the data read command and the plurality of meta data.

Abstract: A memory device to search for a voltage optimized to read a group of memory cells. In response to a read command, the memory device measures first signal and noise characteristics of the memory cells by reading the memory cells at first test voltages. Based on the first signal and noise characteristics, the memory device may determine that the optimized read voltage is outside of a range of the first test voltages. In response, the memory device determines, based on the first signal and noise characteristics, an estimate of the optimized read voltage, and measures second signal and noise characteristics by reading at second test voltages configured around the estimate. The optimized read voltage can be computed based at least in part on the second signal and noise characteristics. The memory device retrieves data from the memory cells using the optimized read voltage.

Abstract: An example apparatus for memory addressing can include an array of memory cells. The apparatus can include a memory cache configured to store at least a portion of an address mapping table. The address mapping table can include a number of regions corresponding to respective amounts of logical address space of the array. The address mapping table can map translation units (TUs) to physical locations in the array. Each one of the number of regions can include a first table. The first table can include entries corresponding to respective TU logical address of the respective amounts of logical address space, respective pointers, and respective offsets. Each one of the number of regions can include a second table. The second table can include entries corresponding to respective physical address ranges of the array. The entries of the second table can include respective physical address fields and corresponding respective count fields.

Abstract: Methods, systems, and computer program products for queue management are provided. Aspects include receiving a first queue entry and storing the first queue entry in a queue at a first location, wherein the first queue entry includes a first target destination, receiving a second queue entry and storing the second queue entry in the queue at a second location, wherein the second queue entry includes a second target destination, tracking a relative age for each of the first queue entry and the second queue entry, transmitting the first queue entry to the first target destination based at least in part on the relative age for the first queue entry being greater than the relative age for the second queue entry, and receiving a third queue entry and storing the third queue entry in the queue at the first location.

Abstract: Embodiments of the disclosed technology relate to a memory system, a memory controller, and an operation method of the memory system. According to embodiments of the present disclosure, the memory system may calculate a time period T1 that is between a beginning of a program operation on a memory page included in the memory device and a suspension of the program operation, may calculate a time period T2 that is between the suspension of the program operation and a time point that is before a resumption of the program operation, may calculate, based on the time period T1 and the time period T2, a read offset voltage to be applied to the memory cell to mitigate the change of the threshold voltage distribution, and may store the read offset voltage in the memory page in the memory device before the resumption of the program operation. Accordingly, the memory system is able to improve the reliability of operations of suspending and resuming a program operation and to improve the performance of a read operation.

Abstract: Memory management unit (MMU) in an application processor responds to an access request, corresponding to inspection request, including target context and target virtual address and the inspection request is for translating the target virtual address to a first target physical address. The MMU includes context cache, translation cache, invalidation queue and address translation manager (ATM). The context cache stores contexts and context identifiers of the stored contexts, while avoiding duplicating contexts. The translation cache stores first address and first context identifiers second addresses, the first address corresponds to virtual address, the first context identifiers corresponds to first context, and the second addresses corresponds to the first address and the first context. The invalidation queue stores at least one context identifier to be invalidated, of the context identifiers stored in the translation cache. The ATM controls the context cache, the translation cache and the invalidation queue.

Abstract: A system includes a synchronizer circuit configured to monitor a first bus coupled between a memory and a first device to determine an occupancy threshold of the memory based on one or more write requests from the first device. The synchronizer circuit monitors a second bus between the memory and a second device to receive a first read transaction of a read request from the second device. The synchronizer circuit determines that the first read transaction is allowed to be sent to the memory based on the occupancy threshold of the memory. In response to the determination, the first read transaction is sent to the memory.

Abstract: It is possible to reduce the latency attributable to memory protection in shared memory systems by performing access protection at a central Data Ownership Manager (DOM), rather than at distributed memory management units in the central processing unit (CPU) elements (CEs) responsible for parallel thread processing. In particular, the DOM may monitor read requests communicated over a data plane between the CEs and a memory controller, and perform access protection verification in parallel with the memory controller's generation of the data response. The DOM may be separate and distinct from both the CEs and the memory controller, and therefore may generally be able to make the access determination without interfering with data plane processing/generation of the read requests and data responses exchanged between the memory controller and the CEs.