Abstract: Apparatus and method for managing metadata in a data storage device such as a solid-state drive (SSD). The metadata are stored in combined (combo) pages in a non-volatile memory (NVM) each having first and second level map entries. The second level map entries provide a logical-to-physical address translation layer for user data blocks stored to the NVM, and the first level map entries describe the second level map entries in the combo page. A global map structure is accessed to identify a selected combo page in the NVM associated with a pending access command. The first and second level map entries are retrieved from the combo page, and the second level map entries are used to identify a target location for the transfer of user data blocks to or from the NVM.

Abstract: A method of operating a storage device includes receiving, at the storage device, a meta information transfer command based on a data read request. The meta information transfer command is received from a host device. The method further includes receiving, at the storage device, a data read command corresponding to the data read request and the meta information transfer command. The data read command is received from the host device. The method further includes receiving, at the storage device, a plurality of meta data corresponding to the data read request and the meta information transfer command. The plurality of meta data is received from the host device. The method further includes performing a data read operation, at the storage device, based on the data read command and the plurality of meta data.

Abstract: According to one embodiment, a memory system includes a nonvolatile memory and a controller which controls the nonvolatile memory. The controller notifies to an outside an extensive signal which indicates a predetermined state of the nonvolatile memory or the controller.

Abstract: Provided are a GPU and a method of managing a memory address thereby. TLBs are configured using an SRAM and an STT-MRAM so that a storage capacity is significantly improved compared to a case where a TLB is configured using an SRAM. Accordingly, the page hit rate of a TLB can be increased, thereby improving the throughput of a device. Furthermore, after a PTE is first written in the SRAM, a PTE having high frequency of use is selected and moved to the STT-MRAM. Accordingly, an increase in TLB update time which may occur due to the use of the STT-MRAM having a low write speed can be prevented. Furthermore, a read time and read energy consumption can be reduced.

Abstract: A write request comprising a logical address, a payload, and an indicator reflecting the character of the payload is received from an application. Based on the indicator, a value of a parameter associated with storing the payload on one or more of a plurality of memory devices is identified. The value of the parameter is determined to satisfy a criterion associated with a particular memory device of the plurality of memory devices. The payload is stored on the particular memory device.

Abstract: First data is received from a first host system and second data is received from a second host system. A composite signal is generated to represent both the first data received from the first host system and the second data received from the second host system. The composite signal comprises a series of signal pulses at multiple levels. A first level and a second level in the composite signal represent values from the first data received from the first host system. A third level and a fourth level in the composite signal represent values from the second data received from the second host system. The composite signal is provided to the memory device.

Abstract: Certain embodiments described herein relate to an improved synthetic full backup image generation system. In some embodiments, one or more components in an information management system can identify a file-server-created backup copy in a particular backup format of a plurality of backup formats, determine structure information associated with the particular backup format, and generate a synthetic full backup copy according to the structure information, where the synthetic full backup copy is also in the particular backup format identical to that of the file-server-created backup copy.

Abstract: A first command directed to a first package of a plurality of memory packages, wherein the first command is issued to a command processor to be applied to the first package is received. A total number of pending commands directed to the first package satisfies a first threshold criterion is determined. Responsive to determining that the total number of pending commands directed to the first package satisfies the first threshold criterion, whether a second command directed to a second package is requesting transmission is determined. Responsive to the second command directed to the second package is requesting transmission, whether the first command comprises a write command is determined. Responsive to determining that the first command comprises a write command, execute a command directed to the second package.

Abstract: In an embodiment, a system may support programmable hashing of address bits at a plurality of levels of granularity to map memory addresses to memory controllers and ultimately at least to memory devices. The hashing may be programmed to distribute pages of memory across the memory controllers, and consecutive blocks of the page may be mapped to physically distant memory controllers. In an embodiment, address bits may be dropped from each level of granularity, forming a compacted pipe address to save power within the memory controller. In an embodiment, a memory folding scheme may be employed to reduce the number of active memory devices and/or memory controllers in the system when the full complement of memory is not needed.

Abstract: The present technology provides a method of operating a host communicating with a memory system including a journal area and a data area. The method of operating the host includes determining to update old data stored in the memory system, transferring, to the memory system, a write command for writing journal data and meta journal data for updating the old data to the journal area, and transferring, to the memory system, a write command for writing new data corresponding to the journal data to the data area in response to a write completion of the meta journal data and the journal data received from the memory system. Each of the meta journal data and the journal data includes a descriptor identifier (ID) indicating the same write transaction.

Abstract: At least one address scheduling method includes selecting a first bit line, selecting a first string connected to the first bit line, performing address scheduling on N pages of each of multi-level cells in the first string sequentially from a bottom word line to a top word line, and after completing the address scheduling on all word lines in the first string, performing address scheduling on second to k-th strings sequentially in the same manner as performed with respect to the first string, where “k” is 2 or a natural number greater than 2.

Abstract: An electronic device comprises a processor, a memory, a memory controller for controlling access to the memory, a hardware security module, and a bus system, to which the processor, the memory controller, and the hardware security module are connected. The hardware security module uses its connection to the bus system to detect requests on the bus system that are sent by the processor. The hardware security module has a secure state and a non-secure state. When in the secure state, the hardware security module adds a secure-state signal to requests sent by the processor over the bus system. The memory controller determines whether memory-access requests include the secure-state signal, and denies access to a secure region of the memory in response to receiving memory-access requests that do not include the secure-state signal.

Abstract: A memory system includes a nonvolatile memory that stores table data and a memory controller for writing and reading data to and from the nonvolatile memory. The memory controller includes a volatile memory that can be in either a retention state during which power is supplied thereto or a power down state during which the power supplied thereto is cut off, a timer that measures elapsed time starting from when the memory system transitions to the low power state, and a register in which previously measured elapsed times are stored, and in which a current measured elapsed time is stored when the memory system wakes up from the low power state. The controller controls the transitioning of the volatile memory from the retention state to the power down state, if the measured elapsed time is greater than a threshold value, which is calculated based on the previously measured elapsed times.

Abstract: A storage system and method for time-based data retrieval are provided. In one embodiment, a controller of the storage system is configured to receive time information from a host; receive a write command from the host, wherein the write command comprises a logical block address; and create a time-to-logical-block-address map from the time information and the logical block address received from the host. Other embodiments are provided.

Abstract: A data storage device includes a memory device and a memory controller. The memory controller is configured to configure a predetermined memory block as an active memory block to receive data from a host device and update content of a sub-region bit table in response to a write operation of the active memory block. The sub-region bit table includes one or more bits, each bit is associated with one or more sub-regions and a value of each bit is initially set to a default value. When data of a first logical address received from the host device is written in the active memory block, the memory controller is configured to determine which sub-region the first logical address belongs to and set the value of the bit associated with the sub-region that the first logical address belongs to to a predetermined value different from the default value.

Abstract: Migrating data in a storage array that includes a plurality of storage devices, including: detecting, by the storage array, an occurrence of a storage device evacuation event associated with one or more source storage devices; responsive to detecting the occurrence of the storage device evacuation event, identifying, by the storage array, one or more target storage devices for receiving data stored on the one or more source storage devices; reducing, by the storage array, write access to the one or more source storage devices; and migrating the data stored on the one or more source storage devices to the one or more target storage devices.

Abstract: Aspects of a storage device including a memory and a controller are provided that allow for storage of tags identifying data types and sequence numbers with data to facilitate data recovery and system integrity checks following a power failure or other system failure event. The controller is configured during a write operation to include a tag in the data identifying the data type as a host write, a recycle write, or another internal write. Following a system failure event, the controller is configured to read the tags to identify the data type in the write. Based on the tags, the controller is configured to properly rebuild or update a logical-to-physical (L2P) table of the storage device to assign correct logical addresses to the most recent data during data recovery, as well as to verify correct logical addresses during system integrity checks.

Abstract: Aspects relate to Input/Output (IO) Memory Management Units (MMUs) that include hardware structures for implementing virtualization. Some implementations allow guests to setup and maintain device IO tables within memory regions to which those guests have been given permissions by a hypervisor. Some implementations provide hardware page table walking capability within the IOMMU, while other implementations provide static tables. Such static tables may be maintained by a hypervisor on behalf of guests. Some implementations reduce a frequency of interrupts or invocation of hypervisor by allowing transactions to be setup by guests without hypervisor involvement within their assigned device IO regions. Devices may communicate with IOMMU to setup the requested memory transaction, and completion thereof may be signaled to the guest without hypervisor involvement. Various other aspects will be evident from the disclosure.

Abstract: Storage management techniques involve: acquiring target data in a target storage page in a memory; determining, based on the target data, check information and identification information associated with the target data, the check information being used to verify whether the target data is correct and the identification information being used to identify the target data; and determining, based on the identification information, storage information associated with the target data and the check information, the storage information indicating whether to store the target data and the check information to a persistent storage device. Therefore, the processing efficiency can be improved, and the input/output (I/O) performance can be improved.

Abstract: Systems and processes for efficient accessing, storing and transmitting of fixed data elements and dynamic data elements, each having its own native form. The data elements are organized according to a schema, with (a) all fixed data elements stored in their native forms in a fixed memory allocation, and (b) each dynamic data element stored in memory in its own native form, in its own data allocation. With this memory structure, computational overhead of converting data elements from their native forms to JSON, XML or other markup language is avoided, making accessing data (getting), updating data (setting), converting data to a serial stream for transmission or other manipulation (serializing), deserializing, and other manipulations of the data elements much more CPU efficient and requiring less bandwidth.