Abstract: Technologies for media management for column-based memory systems include a memory controller including an indirection table. The memory controller receives a memory access to a column-addressable memory indicative of a memory row address. The memory controller determines a logical sub-block identifier based on the memory row address and looks up a physical sub-block identifier in the indirection table. The memory controller issues a redirected memory access indicative of the physical sub-block identifier to the column-addressable memory. The memory access may include a column read. The memory controller may perform a media management operation by copying or moving data from a source physical sub-block to a destination physical sub-block. The memory controller updates the indirection table with the destination physical sub-block for the associated logical sub-block identifier. Other embodiments are described and claimed.

Abstract: Power consumption can be reduced by selective memory chip hibernation. For example, a computing device can allocate first data associated with a first processing operation of a user device to a first chip of a dynamic random access memory (DRAM) of the user device. The computing device can allocate second data associated with a second processing operation of the user device to a second chip of the DRAM of the user device. The computing device can determine the first processing operation has been inactive for a predetermined period of time and migrate the first data from the first chip of the DRAM to a storage device of the user device. The computing device can hibernate the first chip of the DRAM while maintaining power to the second chip of the DRAM for continuing to perform the second processing operation.

Abstract: A request node is provided, that includes request circuitry for issuing outgoing memory access requests to a remote node. Status receiving circuitry receives statuses regarding remote memory access requests at the remote node and control circuitry controls at least one of a rate or an aggression at which the outgoing memory access requests are issued to the remote node in dependence on at least some of the statuses. The control circuitry is inhibited from controlling the rate or the aggression until multiple statuses are received.

Abstract: A storage system and method for retention-based zone determination are provided. In one embodiment, a storage system is presented comprising a memory comprising a plurality of blocks and a controller. The controller is configured to receive, from a host, a zone-create command comprising a health requirement; and in response to receiving the zone-create command, create a zone of memory from blocks of the memory that satisfy the health requirement. Other embodiments are provided.

Abstract: Methods, systems, and devices for dynamic logical page sizes for memory devices are described. A memory device may use an initial set of logical pages each having a same size and one or more logical-to-physical (L2P) tables to map logical addresses of the logical pages to the physical addresses of corresponding physical pages. As commands are received from a host device, the memory device may dynamically split a logical page to introduce smaller logic pages if the host device accesses data in chunk sizes smaller than the size of the logical page that is split. The memory device may maintain one or more additional L2P tables for each smaller logical page size that is introduced, along with one or more pointer tables to map between L2P tables and entries for larger logical page sizes and L2P tables and entries associated with smaller logical page sizes.

Abstract: Memory transactions in a computing device may be scheduled by forming subsets of a set of memory transactions corresponding to memory transaction requests directed to a DRAM. Each subset may include transactions identified by the same combination of direction (read or write) and DRAM rank as each other. The transactions selected for inclusion in each subset may be determined based on efficiency. One of the subsets may be selected based on a metric applied to each subset, and the transactions in the selected subset may be sent to the DRAM.

Abstract: Techniques for performing forward error correction of data to be transmitted over an optical communications channel. The techniques include: receiving data bits; organizing the data bits into an arrangement having a plurality of blocks organized into rows and columns and into a plurality of strands including a first strand of blocks that includes a back portion comprising a first row of the plurality of blocks, and a front portion comprising blocks from at least two different columns in at least two different rows other than the first row of blocks; and encoding at least some of the data bits in the arrangement using a first error correcting code at least in part by generating first parity bits by applying the first error correcting code to first data bits in the front portion of the first strands and second data bits in the back portion of the first strand.

Abstract: Embodiments of the present disclosure provide devices, techniques, and configurations for network interface controllers (NICs) that log write packets received from a network in non-volatile random access memory (NVRAM). In one embodiment, a NIC includes a network interface to couple a host of the NIC to a network, a NVRAM, and a controller coupled with the network interface and the NVRAM, where the controller is to log write packets received at the network interface from the network in the NVRAM. Other embodiments may be described and/or claimed.

Abstract: Embodiments of the present disclosure relate to a memory system and a memory controller, in which data input/output terminals in different data input/output terminal groups corresponding to different channels may be arranged adjacent to each other, thereby preventing skew of a signal occurring during data input/output operations and interference between different signals and reducing the cost required for implementing the memory system.

Abstract: A memory controller includes a memory request queue that stores a memory request associated with a memory device including the first memory die and the second memory die having a shared channel, an address converter that selects one of first and second address mapping tables for the first memory die and the second memory die based on a bit of a physical address of the memory request and converts the physical address into a memory address based on the selected address mapping table and a physical layer that transmits the memory address to the memory device through the channel.

Abstract: In one embodiment, a processor comprises: a first configuration register to store a pointer to a process address space identifier (PASID) table; and an execution circuit coupled to the first configuration register. The execution circuit, in response to a first instruction, is to obtain command data from a first location identified in a source operand of the first instruction, obtain a PASID table handle from the command data, access a first entry of the PASID table using the pointer from the first configuration register and the PASID table handle to obtain a PASID value, insert the PASID value into the command data, and send the command data to a device coupled to the processor. Other embodiments are described and claimed.

Abstract: Scalable virtual memory metadata management comprising a plurality of pre-instantiated VM metadata containers representing the entire amount of real physical memory available to a computing system, with additional instantiated VM metadata containers created as needed. Individual and/or groups of VM metadata containers are assigned to metadata container groups, wherein each container group is controlled by an acquired lock assigned to the VM metadata container groups. Virtual memory metadata is managed using a “least used” technique. In response to allocation requests, the allocator scans the container groups/VM containers and fulfills memory object metadata allocation to the least used VM metadata container of the least used container group, filling the individual VM metadata containers and/or the container groups at a nearly equal rate.

Abstract: A rewriting process of data stored in a control device is performed while executing a normal process. In a control system including a plurality of control devices in which data have been stored, each of which is a device for controlling an electric component of an automobile, a first communication line interconnecting the plurality of control devices, and a second communication line interconnecting the plurality of control devices for hacking up the first communication line, a rewriting device in which rewriting data have been stored is connected to the second communication line, and the rewriting device rewrites data stored in the control device to be rewritten with the rewriting data based on the rewriting data using the second communication line.

Abstract: A memory device comprises a first region configured as non-zoned addressable memory and a second region configured as a zone namespace. A write command comprising a payload and a functional designation of the payload is received, wherein the functional description indicates whether the payload comprises sequentially-writable data. Based on the functional designation of the payload, a corresponding one of the first region or the second region of the memory device is determined, wherein the second region is to store sequentially-writable data. The payload is stored in the corresponding one of the first region or the second region of the memory device.

Abstract: Systems, apparatus and methods are provided for using a partial logical-to-physical (L2P) address translation table for multiple namespaces to perform address translation. An exemplary embodiment may provide a method comprising: receiving a request for a first logical data address (LDA) that belongs to a first namespace (NS); searching the first NS in an entry location table (ELT) for all namespaces whose L2P entries always reside in memory; determining that the first NS is not in the ELT; searching a cache of lookup directory entries of recently accessed translation data units (TDUs) for a first TDU containing a L2P entry for the first LDA; determining that there is a cache miss; retrieving the lookup directory entry for the first TDU from an in-memory lookup directory and determining that it is not valid; reserving a TDU space for the first TDU; and generating a load request for the first TDU.

Abstract: Exemplary methods, apparatuses, and systems include reading logical-to-physical (L2P) table entries from non-volatile memory into volatile memory. Upon detection of a trigger to recover L2P data that was unmerged with the L2P table entries, a copy of an L2P journal is read from non-volatile memory. The L2P journal includes the L2P data that was unmerged with the L2P table entries. One or more of the L2P table entries are updated using the L2P data from the L2P journal.

Abstract: An apparatus comprises transaction handling circuitry to issue memory access transactions, each memory access transaction specifying an epoch identifier indicative of a current epoch in which the memory access transaction is issued; transaction tracking circuitry to track, for each of at least two epochs, a number of outstanding memory access transactions issued in that epoch; barrier termination circuitry to signal completion of a barrier termination command when the transaction tracking circuitry indicates that there are no outstanding memory access transactions remaining which were issued in one or more epochs preceding a barrier point; and epoch changing circuitry to change the current epoch to a next epoch, in response to a barrier point signal representing said barrier point. This helps to reduce the circuit area overhead for tracking completion of memory access transactions preceding a barrier point.

Abstract: A processing device of a memory sub-system can monitor a plurality of received commands to identify a forced unit access command. The processing device can identify a metadata area of the memory device based on the forced unit access command. The processing device can also perform an action responsive to identifying a subsequent forced unit access command to the metadata area.

Abstract: A memory appliance may be provided comprising a processor, a communication interface, a memory, and a region access unit. The memory may be configured in an address space addressable by the processor. The communication interface may be configured to provide the client access to the region of the memory via client-side memory access before initialization of all of the region. A method to create a virtual copy of memory accessible by client-side memory access is also provided. A system may be provided that memory maps at least a portion of a file to a memory region, wherein a virtual address addressable is generated, and the at least a portion of file is accessible through the memory region at the virtual address. The virtual address may be registered with the communication interface, where registration of the virtual address provides client-side memory access to the memory region.

Abstract: A memory appliance may be provided comprising a processor, a communication interface, a memory, and a region access unit. The memory may be configured in an address space addressable by the processor. The communication interface may be configured to provide the client access to the region of the memory via client-side memory access before initialization of all of the region. A method to create a virtual copy of memory accessible by client-side memory access is also provided. A system may be provided that memory maps at least a portion of a file to a memory region, wherein a virtual address addressable is generated, and the at least a portion of file is accessible through the memory region at the virtual address. The virtual address may be registered with the communication interface, where registration of the virtual address provides client-side memory access to the memory region.