Abstract: A method is provided for storing data from an external device in a dynamoelectric machine assembly (i.e., an electric motor or generator). The dynamoelectric machine assembly includes a memory device and a processor for controlling operation of the dynamoelectric machine assembly in response to commands from an external device. The method includes receiving a command from the external device to store data in the memory device of the dynamoelectric machine assembly, and storing the data in the memory device in response to the command. Dynamoelectric machine assemblies, external devices and systems suitable for use in the provided method are also disclosed.

Abstract: Techniques to automatically allocate resources among storage system resource consumers are disclosed. In various embodiments, for each of a plurality of heterogeneous categories of resource consumer of the storage system a corresponding allocated portion of storage system resources to be available for use to perform operations associated with that category of resource consumer is determined. A storage system is configured automatically to provide access to resources of the storage system based at least in part on the respective portions of storage system resources allocated to each category of resource consumer, including by ensuring availability to workloads associated with each category at any given time at least a minimum amount of storage system resources corresponding to the portion of storage system resources allocated to that category.

Abstract: Embodiments are directed to techniques for enforcing prerequisite conditions on a data object for an operational feature both upon initiation of that operational feature and while that operational feature is maintained. Accordingly, improved techniques enforce conditions by setting a flag associated with a data object upon confirming that the conditions have been met and checking the flag anytime a configuration change to the data object is requested that would cause the conditions to be violated. If the flag is set, any configuration change that would cause the conditions to be violated is rejected.

Abstract: Providing for address translation in a virtualized system environment is disclosed herein. By way of example, a memory management apparatus is provided that comprises a shared translation look-aside buffer (TLB) that includes a plurality of translation types, each supporting a plurality of page sizes, one or more processors, and a memory management controller configured to work with the one or more processors. The memory management controller includes logic configured for caching virtual address to physical address translations and intermediate physical address to physical address translations in the shared TLB, logic configured to receive a virtual address for translation from a requester, logic configured to conduct a table walk of a translation table in the shared TLB to determine a translated physical address in accordance with the virtual address, and logic configured to transmit the translated physical address to the requester.

Abstract: A data storage device includes a memory and a controller. The memory includes a first partition and a second partition. The controller includes a pattern detector that is configured to detect one or more tags in data from an access device to be stored in the first partition. The controller is configured to generate, in the second partition, one or more links to the data that is stored in the first partition, the one or more links organized according to metadata associated with the one or more tags.

Abstract: A memory device performing an internal copy operation is provided. The memory device may receive a source address, a destination address, and page size information together with an internal copy command, compares the source address with the destination address, and performs an internal copy operation. The internal copy operation may be an internal block copy operation, an inter-bank copy operation, or an internal bank copy operation. The internal copy operation may be performed with respect to one-page data, half-page data, or quarter-page data, based on the page size information. The memory device may output as a flag signal a copy-done signal indicating that the internal copy operation has been completed.

Abstract: A method for providing state inheritance across command lists in a multi-threaded processing environment. The method includes receiving an application program that includes a plurality of parallel threads; generating a command list for each thread of the plurality of parallel threads; causing a first command list associated with a first thread of the plurality of parallel threads to be executed by a processing unit; and causing a second command list associated with a second thread of the plurality of parallel threads to be executed by the processing unit, where the second command list inherits from the first command list state associated with the processing unit.

Abstract: Systems, methods and/or devices are used to enable prioritizing garbage collection and block allocation based on I/O history for logical address regions. In one aspect, the method includes (1) receiving, at a storage device, a plurality of input/output (I/O) requests from a host, the plurality of I/O requests including read requests and write requests to be performed in a plurality of regions in a logical address space of the host, (2) in accordance with the plurality of I/O requests over a predetermined time period, identifying an idle region of the plurality of regions in the logical address space of the host, and (3) in accordance with the identification of the idle region, enabling garbage collection of data storage blocks, in the storage device, that store data in the idle region.

Abstract: Disclosed herein are a buffer cache apparatus, a journaling file system, and a journaling method capable of incorporating journaling features based on nonvolatile memory. The buffer cache apparatus provides a data buffering function between a central processing unit (CPU) and storage. The buffer cache apparatus includes a plurality of cache blocks and a journal management unit. The plurality of cache blocks are configured as volatile or nonvolatile memory devices. The journal management unit maintains states of freezing for write-protecting dirty up-to-date cache blocks among the plurality of cache blocks.

Abstract: Systems, methods and/or devices are used to enable using history of I/O sequences to trigger cached read ahead in a non-volatile storage device. In one aspect, the method includes (1) receiving, at a storage device, a plurality of input/output (I/O) requests from a host, the plurality of I/O requests including read requests and write requests to be performed in a plurality of regions in a logical address space of the host, and (2) performing one or more operations for each region of the plurality of regions in the logical address space of the host, including (a) determining whether the region has a history of sequential read requests during a predetermined time period, and (b) in accordance with a determination that the region has a history of sequential read requests during the predetermined time period, enabling read ahead logic for the region.

Abstract: A memory controller includes a scheduler that decides a processing order of a plurality of requests provided from an external device with reference to a timing parameter value for each of the requests; and a timing control circuit that adjusts the timing parameter value according to a corresponding address to access a memory device, the corresponding address being used to process a corresponding request of the plurality of requests.

Abstract: A memory controller includes a data modulator and a data demodulator. The data modulator is configured to translate original data into modified data according to a conversion operation and write the modified data to the array of memory locations. The modified data generated by the conversion operation reduces a likelihood of the original data suffering a read disturb in the array of memory locations.

Abstract: A storage controller is configured to implement an atomic storage operation comprising a plurality of separate storage operations on a non-volatile storage medium. The storage controller may store persistent indicators to identify data that pertains to the atomic storage operation. An invalid shutdown may occur before the atomic storage operation is complete. A restart and recovery operation comprises a first scan of the non-volatile storage medium to identify data of the failed atomic storage operation. A physical trim note is stored on the non-volatile storage medium to identify the data of the failed atomic storage operation. The data may be identified by media address. Storage metadata is reconstructed in a second scan, which excludes the data and/or operations of the failed atomic storage operation.

Abstract: Systems and methods for managing regular maintenance operations in combination with infrequent extended maintenance operations in a non-volatile memory are disclosed. The method may include executing portions of the extended maintenance over the course of multiple regular maintenance operations. A memory system may include non-volatile memory and a controller configured to execute one or more of the steps of selecting a previously programmed source block for an extended maintenance operation, sequentially selecting a plurality of previously programmed blocks for regular maintenance operations and dividing execution of the extended maintenance operation up such that the extended maintenance operation is completed in parts across the plurality of regular maintenance operations.

Abstract: Techniques are disclosed relating to managing data-request dependencies for a cache. In one embodiment, an integrated circuit is disclosed that includes a plurality of requesting agents and a cache. The cache is configured to receive read and write requests from the plurality of requesting agents including a first request and a second request. The cache is configured to detect that the first and second requests specify addresses that correspond to different portions of the same cache line, and to determine whether to delay processing one of the first and second requests based on whether the first and second requests are from the same requesting agent. In some embodiments, the cache is configured to service the first and second requests in parallel in response to determining that the first and second requests are from the same requesting agent.

Abstract: Systems and methods for balancing maintenance and programming host data across multiple maintenance source blocks in a non-volatile memory are disclosed. A memory system may include non-volatile memory and a controller configured to execute one or more of the steps of selecting a fixed plurality of maintenance source blocks for executing a balance cycle of maintenance and host writes across the selected fixed plurality of maintenance source blocks. The method interleaves moving of valid data from source blocks with host data writes to achieve a balance of free space generation and consumption for the balance cycle, while periodically reevaluating an overall interleave ratio and/or substituting other previously programmed blocks for one of the previously selected plurality during the balance cycle.

Abstract: A storage device includes a nonvolatile memory device including a plurality of memory cells, the memory cells divided into a plurality of pages, and a controller configured to control the nonvolatile memory device. The storage device is configured to collect two or more write data groups to be written to two or more pages, to simultaneously perform a common write operation with the two or more pages based on the two or more write data groups, and to sequentially perform an individual write operation with each of the two or more pages based on the two or more write data groups.

Abstract: Systems, methods and/or devices are used to enable identification of hot regions to enhance performance and endurance of a non-volatile storage device. In one aspect, the method includes (1) receiving a plurality of input/output (I/O) requests to be performed in a plurality of regions in a logical address space of a host, and (2) performing one or more operations for each region of the plurality of regions in the logical address space of the host, including (a) determining whether the region is accessed by the plurality of I/O requests more than a predetermined threshold number of times during a predetermined time period, (b) if so, marking the region with a hot region indicator, and (c) while the region is marked with the hot region indicator, identifying open blocks associated with the region, and marking each of the identified open blocks with a hot block indicator.

Abstract: A device includes a memory and a controller coupled to the memory. The controller is configured to maintain a first address translation table associated with the memory and a second address translation table associated with the memory. The controller is further configured to receive a command to erase the memory. The controller is further configured to switch an indicator of an active address translation table from the first address translation table to the second address translation table in response to receiving the command.

Abstract: Methods, devices, and systems for data signal mirroring are described. One or more methods include receiving a particular data pattern on a number of data inputs/outputs of a memory component, and responsive to determining that a mirrored version of the particular data pattern is received by the memory component, configuring the number of data inputs/outputs to be mirrored.