Abstract: A storage device includes a plurality of nonvolatile memories and a controller. The plurality of nonvolatile memories are configured to distributively store first and second stripes of a stripe set. The controller includes a first memory and a second memory within the controller. The controller is configured to receive the first and second stripes from a host, distributively store the first and second stripes in the plurality of nonvolatile memories, and to perform a parity operation based on the first and second stripes. The controller is configured to generate intermediate parity based on the first stripe and store the intermediate parity in the first memory. If the parity operation is stopped, the controller is configured to move the intermediate parity stored in the first memory to the second memory.

Abstract: A network sensor that features a data store and a packet processing engine. Communicatively coupled to the data store, the packet processing engine is configured to (i) generate a retention priority for at least a first flow within a first storage region of a plurality of storage regions and (ii) identify, in response to an eviction request, the priority of each of the plurality of storage regions. The priority of the first storage region is partially based on the retention priority associated with the first flow while the priority of a second storage region is based on retention priorities associated with flows stored within the second storage region. The packet processing engine also is configured to identify, through use of the retention priorities of the stored flows within the first storage region, which flows are to be retained and which flows are to be evicted.

Abstract: A system and method include receiving, by an object store virtual machine of a virtual object storage system, a user request for updating an element of an object store. The user request includes a first compare and swap value. The system and method also include updating the first compare and swap value from the second user request for obtaining an updated compare and swap value, comparing the updated compare and swap value with a current compare and swap value of the element, and updating the element upon determining that the updated compare and swap value is greater than the current swap and compare value. Updating the element comprises one of creating a new version of the element and overwriting a previous version of the element. The system and method further include replacing the current compare and swap value with the updated compare and swap value.

Abstract: Embodiments of systems, apparatuses, and methods for temporarily allowing access to a lower privilege level from a higher privilege level.

Abstract: The disclosure provides a memory management method, which includes: selecting at least one logical unit mapped to physical units programmed based on a first operating mode; determining a reference count according to a number of the selected logical unit; receiving a first write command; determining whether the reference count is greater than a threshold value; if the reference count is greater than the threshold value, programming first data into a first physical unit based on the first operating mode, and each memory cell in the first physical unit stores a first number of bit data; if the reference count is not greater than the threshold value, programming the first data into a second physical unit based on a second operating mode, and each memory cell in the second physical unit stores a second number of bit data, and the second number is greater than the first number.

Abstract: A system and method is provided for managing computing resources of a physical server executing a plurality of virtual machines (VMs) including a first virtual machine (VM). The first VM executes a guest block device driver configured to provide a guest operating system of the first VM an interface to a memory-mapped virtual storage device. A virtual machine monitor maintains a disk cache associated with the virtual storage device. The disk cache resides in a host physical memory of the physical server outside of portions of the host physical memory associated with guest physical memory of the first VM. The virtual machine monitor is configured to, responsive to determining that available host physical memory satisfies a threshold condition, reclaim a target portion of the host physical memory allocated to the disk cache.

Abstract: A storage device may include: a protocol processing unit suitable for communicating with a host based on a predetermined protocol, and transferring a response signal to at least one status request signal that is received from the host; a power management unit suitable for supplying a power source voltage, and outputting a detection signal which represents a low voltage detection status where the power source voltage has a voltage level lower than a predetermined voltage level; and a core unit suitable for blocking a transfer of the response signal by the protocol processing unit in response to the detection signal, and processing at least one task request which is received from the host through the protocol processing unit after the blocking.

Abstract: Embodiments of this disclosure allow non-position-independent-code to be shared between a closed application and a subsequent application without converting the non-position-independent-code into position-independent-code. In particular, embodiment techniques store live data of a closed application during runtime of the closed application, and thereafter page a portion of the live data that is common to both the closed application and a subsequent application back into volatile memory at the same virtual memory address in which the portion of live data was stored during runtime of the closed application so that the paged lived data may be re-used to execute the subsequent application in the managed runtime environment. Because the paged live data is stored at the same virtual memory address during the runtimes of both applications, non-position-independent-code can be shared between the applications.

Abstract: In a computer system having virtual machines, one or more unused bits of a guest physical address range are allocated for aliasing so that multiple virtually addressed sub-pages can be mapped to a common memory page. When one bit is allocated for aliasing, dirty bit information can be provided at a granularity that is one-half of a memory page. When M bits are allocated for aliasing, dirty bit information can be provided at a granularity that is 1/(2M)-th of a memory page.

Abstract: A memory network includes a first local memory group, a second local memory group, and multiple first channels. The first local memory group includes multiple first memory devices that are not directly connected to each other. The second local memory group includes multiple second memory devices that are not directly connected to each other. The first channels are configured to connect the first memory devices to the second memory devices in a one to one relationship.

Abstract: Embodiments of the present disclosure provide a method and device for storing data. The method comprises: generating a data block corresponding to data to be stored; aligning the data block to a boundary of a tracking unit of a predefined size for validating the data; and storing the aligned data block in at least one storage unit of a storage space, the at least one storage unit having an identical size. The method according to embodiments of the present disclosure can align the data block so as to minimize the waste of storage space and avoid the situation where the rest data cannot be validated due to disappearance of partial data.

Abstract: Inter-process data transfer on a host computing device is disclosed. A kernel module executing on the host computing device receives, from a first process, buffer registration information that identifies a virtual address of a receive buffer and a length of the receive buffer. The kernel module determines a first physical memory address that corresponds to the virtual address of the receive buffer. The kernel module receives, from a second process, a send request to send data to the first process, the send request including a virtual address of a send buffer, a length of the data, and a destination identifier that is associated with the receive buffer. The kernel module determines a second physical memory address that corresponds to the virtual address of the send buffer and transfers the data directly from the second physical memory address to the first physical memory address.

Abstract: A data storage device is disclosed comprising a head actuated over a disk comprising a plurality of tracks. A first degradation metric is maintained for a first segment of a first track, wherein the first degradation metric indicates a degree of degradation for data recorded in the first segment. The first degradation metric is processed to select an access command from a plurality of access commands including a read command to read the first segment. The selected access command is executed to access the disk.

Abstract: Systems, methods and/or devices are used to enable using sub-region I/O history to cache repeatedly accessed sub-regions in a non-volatile storage device. In one aspect, the method includes (1) receiving a plurality of input/output (I/O) requests including read requests and write requests to be performed in a plurality of regions in a logical address space of a host, and (2) performing one or more operations for each region of the plurality of regions in the logical address space of the host, including, for each sub-region of a plurality of sub-regions of the region: (a) determining whether the sub-region is accessed more than a predetermined threshold number of times during a predetermined time period, and (b) if so, caching, from a storage medium of the storage device to a cache of the storage device, data from the sub-region.

Abstract: The present invention discloses a first preferred processor comprising a fixed look-up table circuit (LTC) and a writable LTC. The fixed LTC realizes at least a common function while the writable LTC realizes at least a non-common function. The present invention further discloses a second preferred processor comprising a two-dimensional (2-D) LTC and a three-dimensional (3-D) LTC. The 2-D LTC realizes at least a fast function while the 3-D LTC realizes at least a non-fast function.

Abstract: A method for obtaining and storing monitoring information. The method includes one or more computer processors generating a plurality of data records, based at least in part on a configuration for generating information, wherein the plurality of data records includes a first data record. The method further includes determining that a configuration for analyzing information dictates an analysis of at least a one data record, wherein the at least one data record includes a second data record. The method further includes determining that the plurality of data records do not include the second data record. The method further includes modifying the configuration for generating information to include generating the second data record. The method further includes generating an updated plurality of data records based on the modified configuration for generating information, wherein the updated plurality of data records includes the first data record and the second data record.

Abstract: Reusing data in a memory. A method includes determining to revalidate a first set of data stored in a first, invalidated, portion of the memory. An amount of data in a second set of data in the free portion of the memory that will also be revalidated by revalidating the first portion of the memory is determined. As a result, an action to perform is determined and performed. The action includes either revalidating the first portion of the memory if the amount of data in the second set of data is at or below a predetermined threshold or copying the first set of data in the first portion of the memory, and re-writing the first set of data to the active valid portion of the memory, if the amount of data in the second set of data is above the predetermined threshold.

Abstract: Apparatus and methods for operation of a memory controller, memory device and system are described. During operation, the memory controller transmits a read command which specifies that a memory device output data accessed from a memory core. This read command contains information which specifies whether the memory device is to commence outputting of a timing reference signal prior to commencing outputting of the data. The memory controller receives the timing reference signal if the information specified that the memory device output the timing reference signal. The memory controller subsequently samples the data output from the memory device based on information provided by the timing reference signal output from the memory device.

Abstract: A device includes a non-volatile memory and a controller coupled to the non-volatile memory. The device may be configured according to a mode in which execution of a particular command is unauthorized while the device is configured in the mode. While in the mode, the device may authorize execution of the command to occur during the mod.

Abstract: Techniques to satisfy quality of service (QoS) requirements on a per virtual machine basis natively in a storage system are disclosed. In various embodiments, for each of a plurality of virtual machines a corresponding input/output (I/O) request queue is stored on the storage system. Requests are scheduled to be pulled from the respective request queues and added to a corresponding storage operation pipeline at the storage system in an order determined based at least in part on a per virtual machine quality of service parameter.