Abstract: A method for automatic calibration of read latency of a memory module is envisaged. The read latency is initially set to a default maximum value. The default maximum value is equivalent to the number of clock cycles required to complete a data read operation. A data pattern to be read from the memory module in consideration of the default maximum value is identified. A memory read operation is preformed, and a first data pattern is captured, in accordance with the default maximum value. The identified data pattern is compared with the first data pattern, and the default maximum value is iteratively calibrated based on the comparison thereof. Aforementioned steps are repeated across a plurality of memory read operations, and variations ire the maximum default value are tracked, and an average maximum value is calculated based thereupon. The average maximum value is assigned as the read latency for the memory module.

Abstract: A high performance, low power, and cost effective multiple channel cache-system memory system is disclosed.

Abstract: In response to receipt by a first coherency domain of a memory access request originating from a master in a second coherency domain and excluding from its scope a third coherency domain, coherence participants in the first coherency domain provide partial responses, and one of the coherence participants speculatively provides, to the master, data from a target memory block. The data includes a memory domain indicator indicating whether the memory block is cached, if at all, only within the first coherency domain. Based on the partial responses a combined response is generated representing a systemwide coherence response to the memory access request. In response to the combined response indicating success and the memory domain indicator indicating that a valid copy of the memory block may be cached outside the first coherence domain, the master discards the speculatively provided data and reissues the memory access request with a larger broadcast scope.

Abstract: A method for concurrently erasing data on a processor and preparing the processor for removal from a computing system is disclosed. In one embodiment, such a method includes determining tasks queued to be executed on a processor and reassigning the tasks to a different processor, such as to a different processor in the same cluster as the processor. The method further prevents new tasks from being assigned to the processor. The method waits for currently executing tasks on the processor to complete. Once the currently executing tasks are complete, the method initiates a cache-hostile job on the processor to evict entries in cache of the processor. Once the cache-hostile job is complete, the method enables the processor to be removed from a computing system such as a storage system controller. A corresponding system and computer program product are also disclosed.

Abstract: A storage device includes a nonvolatile semiconductor memory and a controller. The nonvolatile semiconductor memory includes a first region and a second region. The controller classifies a plurality of read requests for reading data from the nonvolatile semiconductor memory into first read requests for reading data from the first region and second read requests for reading data from the second region, pairs one of the first read requests with one of the second read requests to generate a third read request, and outputs the third read request to the nonvolatile semiconductor memory.

Abstract: Techniques to facilitate enhanced addressing of local and network resources from a computing system are provided herein. In one implementation, a method of updating a virtual address mapping for an application on a computing system includes identifying a request to update the address mapping from a first mapping to a second mapping, wherein the first mapping maps virtual addresses to local addresses for local resources. The method further includes identifying at least one configuration resource to support the update, and retrieving an update configuration from the at least one configuration resource. Based on the update configuration, the method provides generating the second mapping, wherein the second mapping maps the virtual addresses to second local addresses for the second local resources and network addresses that address network resources accessible over a network.

Abstract: Systems, methods and/or devices are used to enable real-time I/O pattern recognition to enhance performance and endurance of a storage device. In one aspect, the method includes (1) at a storage device, receiving from a host a plurality of input/output (I/O) requests, the I/O requests specifying operations to be performed in a plurality of regions in a logical address space of the host, and (2) performing one or more operations for each region of the plurality of regions in the logical address space of the host, including (a) maintaining a history of I/O request patterns in the region for a predetermined time period, and (b) using the history of I/O request patterns in the region to adjust subsequent I/O processing in the region.

Abstract: Systems, methods and/or devices are used to enable using history of I/O sizes and I/O sequences to trigger coalesced writes in a non-volatile storage device. In one aspect, the method includes (1) receiving a plurality of input/output (I/O) requests to be performed in a plurality of regions in a logical address space of a host, and (2) performing one or more operations for each region of the plurality of regions in the logical address space of the host, including (a) determining whether the region has a history of I/O requests to access data of size less than a predefined small-size threshold during a predetermined time period, (b) determining whether the region has a history of sequential write requests during the predetermined time period, and (c) if both determinations are true, coalescing subsequent write requests to the region.

Abstract: A main controller in a data storage system having multiple storage devices determines an initial set of memory block candidates for data lifetime operations by receiving from each of a plurality of the storage devices information identifying one or more potential memory block candidates, with respective received memory blocks having been classified by respective storage devices as potential candidates. The main controller determines a set of related memory blocks, and, based on received usage information for the candidate memory blocks and the related memory blocks, selects a target group of memory blocks and initiates performance of the data lifetime operations on the memory blocks of the selected target group.

Abstract: Technology is disclosed herein for aborting a tail portion of a command queue in a storage device. In one aspect, one or more control circuits of a storage system are configured to abort tasks at a tail end of a command queue in response to receiving a task tail abort command. However, tasks at the head end of the command queue may still be executed. Thus, the head end of the command queue need not be rebuilt after the task tail abort command is performed. Therefore, considerable time is saved by not having to rebuild the head end of the command queue. Note that the task tail abort command may be received while the storage system is in a sequential command execution mode, in which tasks are executed in the order of their respective task identifiers.

Abstract: At least one aspect is directed to a NAND flash storage device including a plurality of NAND flash chips and a controller. The controller is configured to receive data over an input/output (I/O) bus and write the received data to a first NAND flash chip of the plurality of NAND flash chips and a second NAND flash chip of the plurality of NAND flash chips. The write operations to each NAND flash chip do not overlap in time. The controller is configured to read data from whichever of the first NAND flash chip or the second NAND flash chip is not currently executing a write operation such that read operations are not queued behind write operations.

Abstract: A method for allocating workloads based on a total cost of ownership (TCO) model includes receiving a workload; estimating a cost for allocating the workload to each disk of disks in a disk pool based on a TCO model; determining a disk among the disks in the disk pool that minimizes a TCO; and allocating the workload to the disk. The TCO model incorporates a plurality of cost factors for estimating costs for each disk in the disk pool for allocating the workload.

Abstract: A storage device uses non-volatile memory devices for caching. The storage device operates in a mode referred to herein as write-back mode. In write-back mode, a storage device responds to a request to write data by persistently writing the data to a cache in a non-volatile memory device and acknowledges to the requestor that the data is written persistently in the storage device. The acknowledgement is sent without necessarily having written the data that was requested to be written to primary storage. Instead, the data is written to primary storage later.

Abstract: Described are dynamic memory systems that perform overlapping refresh and data access (read or write) transactions that minimize the impact of the refresh transaction on memory performance. The memory systems support independent and simultaneous activate and precharge operations directed to different banks. Two sets of address registers enable the system to simultaneously specify different banks for refresh and data-access transactions.

Abstract: Provided is a storage apparatus including a plurality of storage devices which store data, a controller which executes data input/output processing to the storage devices, and a processor which transmits/receives information with the controller, wherein the controller manages a plurality of different tag numbers by separating the tag numbers into a plurality of groups, and upon receiving a first command from the processor, assigns a tag number belonging to one group among the plurality of groups to the first command, and transfers the first command to a designated storage device, and, upon subsequently receiving an instruction for a chip reset from the processor, executes a chip reset, and, upon subsequently receiving a second command from the processor, assigns a tag number belonging to a group which is different from the group used before the chip reset to the second command, and transfers the second command to a designated storage device.

Abstract: A main processor core having a first memory and a sub processor core having a second memory and controlled by the main processor core are included. An operating system is incorporated in the main processor core, and no operating system is incorporated in the sub processor core. Shared memories are formed in the first and second memories, respectively. Data in the shared memories of the first and second memories are synchronized. The main processor core is configured to synchronize the data in the shared memories formed in the first and second memories while the sub processor core stops operating.

Abstract: A storage control system, and a method of operation thereof, including: a recycle write queue for providing a recycle write; a host write queue for providing a host write; and a scheduler, coupled to the recycle write queue and the host write queue, for scheduling the recycle write and the host write for writing to a memory device.

Abstract: A method for operating a data storage device includes providing a nonvolatile memory device including a page divided into a first half page and a second half page; dividing, when receiving data smaller than a size of a page, the data into first and second partial data; generating first and second valid data by adding metadata to the first and second partial data; generating first dummy data to be stored in the first half page together with the first valid data and second dummy data to be stored in the second half page together with the second valid data; storing the first valid data in the first half page and the second valid data in the second half page such that the first and second valid data are successive; and storing the first dummy data in an unused area of the first half page and the second dummy data in an unused area of the second half page.

Abstract: A dynamic premigration protocol is implemented in response to a secondary tier returning to an operational state and an amount of data associated with a premigration queue of a primary tier exceeding a first threshold. The dynamic premigration protocol can comprise at least a temporary premigration throttling level. An original premigration protocol is implemented in response to an amount of data associated with the premigration queue decreasing below the first threshold.

Abstract: A storage device includes a plurality of nonvolatile memories and a controller. The plurality of nonvolatile memories are configured to distributively store first and second stripes of a stripe set. The controller includes a first memory and a second memory within the controller. The controller is configured to receive the first and second stripes from a host, distributively store the first and second stripes in the plurality of nonvolatile memories, and to perform a parity operation based on the first and second stripes. The controller is configured to generate intermediate parity based on the first stripe and store the intermediate parity in the first memory. If the parity operation is stopped, the controller is configured to move the intermediate parity stored in the first memory to the second memory.