Patents Examined by Gautam Sain
  • Patent number: 11194511
    Abstract: Devices and techniques for arbitrating operation of memory devices in a managed NAND memory system to conform the operation to a power budget. In an example, a method can include enabling a subset of memory die of a memory system having multiple memory die, starting an active timer for each active memory die, initializing execution of a buffered memory command at each active die based on a timestamp associated with the buffered memory command, and disabling a first memory die of the subset of memory die when the active timer for the first die expires to maintain compliance with a power budget of the memory system.
    Type: Grant
    Filed: March 5, 2019
    Date of Patent: December 7, 2021
    Assignee: Micron Technology, Inc.
    Inventor: David Aaron Palmer
  • Patent number: 11169725
    Abstract: To reduce the time, cost, and computational resources associated with writing to and reading from a non-volatile memory device multiple times, log data is stored in volatile memory of a computing device. The host device includes a file system that receives the log data from an application when the application sends an instruction to write the log data to the file system. Once the log data is stored in volatile memory, device data indicative of the rate at which log data is received by and transmitted from the computing device, and an amount of unused memory or other computational resources of the computing device, may be used to determine which services are permitted to access the log data, and whether to provide access to all of the log data or only a portion of the log data based on a sampling rate.
    Type: Grant
    Filed: December 11, 2019
    Date of Patent: November 9, 2021
    Assignee: AMAZON TECHNOLOGIES, INC.
    Inventors: Alex Jennifer Tribble, Anil Gangolli, Robert James Hanson, Mohsen Azimi
  • Patent number: 11163499
    Abstract: Embodiments of the present disclosure disclose a method, apparatus and system for controlling mounting of a file system. A specific embodiment of the method includes: receiving network attribute information of a target client sent by a target server as first network attribute information; determining, based on the first network attribute information, whether the target client has permission to mount to a target file system; and sending, in response to determining that the target client has permission to mount to the target file system, an identification of the target file system to the target server.
    Type: Grant
    Filed: September 10, 2019
    Date of Patent: November 2, 2021
    Assignee: BEIJING BAIDU NETCOM SCIENCE AND TECHNOLOGY CO., LTD.
    Inventors: Hongzhou Zhang, Yongqiang Yang
  • Patent number: 11157192
    Abstract: A storage controller receives a request from a host to generate a source dataset by downloading a cloud object corresponding to the source dataset from a cloud storage. A plurality of writers that execute in parallel determines from metadata that indicates a mapping of tracks of the source dataset to tracks of the cloud object, which track of the cloud object corresponds to which track of the source dataset, to generate the source dataset from the cloud object for storing in a storage drive coupled to the storage controller.
    Type: Grant
    Filed: February 20, 2019
    Date of Patent: October 26, 2021
    Assignee: International Business Machines Corporation
    Inventors: Qiang Xie, Hui Zhang, Edward H. Lin
  • Patent number: 11144474
    Abstract: A computational device receives an indication that specifies a maximum retention time in cache for a first plurality of tracks, wherein no maximum retention time is specified for a second plurality of tracks. A plurality of insertions points are generated in a least recently used (LRU) list, wherein different insertion points in the LRU list correspond to different amounts of time that a track of the first plurality of tracks is expected to be retained in the cache, wherein the LRU list is configured to demote both tracks of the first plurality of tracks and the second plurality of tracks from the cache.
    Type: Grant
    Filed: June 26, 2018
    Date of Patent: October 12, 2021
    Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Lokesh M. Gupta, Joseph Hayward, Kyler A. Anderson, Matthew G. Borlick
  • Patent number: 11138124
    Abstract: A computer-implemented method, according to one embodiment, includes: determining whether a number of blocks included in a RTU queue associated with a first block pool is in a first predetermined range. In response to determining that the number of blocks included in the RTU queue is not in the first predetermined range, a determination is made as to whether a current I/O workload is in a second predetermined range. In response to determining that the current I/O workload is in the second predetermined range, for each block in the first block pool having a desired amount of metadata associated with the pages in the given block: a subset of pages in the given block are selected and data is relocated therefrom to a block in the second block pool.
    Type: Grant
    Filed: October 30, 2019
    Date of Patent: October 5, 2021
    Assignee: International Business Machines Corporation
    Inventors: Sasa Tomic, Radu Ioan Stoica, Nikolaos Papandreou, Nikolas Ioannou, Roman Alexander Pletka, Aaron Daniel Fry, Timothy Fisher
  • Patent number: 11119683
    Abstract: Generating, in a geographically diverse storage system, a degraded convolved chunk that consumes less storage space than a convolved chunk that is not a degraded chunk is disclosed. The degraded convolved chunk can be generated at a third zone of the storage system and be based on a compressed representation of a first chunk from a first zone of the storage system and a second chunk from a second zone of the storage system, wherein the first chunk is a degraded chunk that comprises at least one non-relevant chunk fragment. In an embodiment, the compressed representation can be generated at the first zone. In another embodiment the compressed representation can be generated at the third zone. In an aspect, mapping data corresponding a logical compression of first chunk fragments to physical storage locations of the first chunk fragments can be employed in data operations of the storage system.
    Type: Grant
    Filed: December 20, 2018
    Date of Patent: September 14, 2021
    Assignee: EMC IP HOLDING COMPANY LLC
    Inventors: Mikhail Danilov, Yohannes Altaye
  • Patent number: 11112981
    Abstract: The invention introduces a method for configuring impedance of memory interfaces, performed by a processing unit, including: setting a first impedance value associated with an on-die termination (ODT) for a receiver of a controller to a first default value; setting a second impedance value associated with a driver variable resistance for a transmitter of a memory device to a second default value; performing tests for test combinations each comprises a third impedance value associated with a driver variable resistance for a transmitter of the controller and a fourth impedance value associated with an ODT for a receiver of the memory device; and storing a test result for each in a predefined location of a static random access memory (SRAM), thereby enabling a calibration host to obtain the test result for each from the SRAM.
    Type: Grant
    Filed: July 2, 2019
    Date of Patent: September 7, 2021
    Assignee: SILICON MOTION, INC.
    Inventors: Wei-Liang Sung, Chi-Ping Chang
  • Patent number: 11113194
    Abstract: The embodiments herein creates DCT mechanisms that initiate a DCT at the time the updated data is being evicted from the producer cache. These DCT mechanisms are applied when the producer is replacing the updated contents in its cache because the producer has either moved on to working on a different data set (e.g., a different task) or moved on to working on a different function, or when the producer-consumer task manager (e.g., a management unit) enforces software coherency by sending Cache Maintenance Operations (CMO). One advantage of the DCT mechanism is that because the direct cache transfer takes place at the time the updated data is being evicted, by the time the consumer begins its task, the updated contents have already been placed in its own cache or another cache within the cache hierarchy.
    Type: Grant
    Filed: September 4, 2019
    Date of Patent: September 7, 2021
    Assignee: XILINX, INC.
    Inventors: Jaideep Dastidar, Millind Mittal
  • Patent number: 11099746
    Abstract: A method for data storage includes, in a network element, receiving from packet-processing circuitry at least a read command and a write command, for execution in a memory array that includes multiple single-port memory banks. When the read command and the write command are to access different memory banks in the memory array, the read command and the write command are executed for the packet-processing circuitry in the different memory banks in a same memory-access cycle. When the read command and the write command are both to access a first memory bank, a second memory bank of the memory array is selected. The read command is executed in the first memory bank and the write command is executed in the second memory bank, in the same memory-access cycle.
    Type: Grant
    Filed: April 7, 2016
    Date of Patent: August 24, 2021
    Assignee: MARVELL ISRAEL (M.I.S.L) LTD.
    Inventors: Dror Bromberg, Roi Sherman
  • Patent number: 11093244
    Abstract: An apparatus includes a memory component, a delay component, and a command component coupled to the delay component. The command component can be configured to enter a received command associated with accessing a physical address in the memory component into an execution queue and mark the command as active. The command component can be configured to send the active command to the memory component to be executed. The command component can be configured to clear the active command from the execution queue in response to receiving a message from the memory component, via the delay component, indicating the active command has been executed. The delay component can be configured to delay the message from the memory component a particular period of time before sending the message to the command component.
    Type: Grant
    Filed: August 28, 2019
    Date of Patent: August 17, 2021
    Assignee: Micron Technology, Inc.
    Inventors: Bruce Dunlop, Gary J. Lucas, Edward C. McGlaughlin
  • Patent number: 11093147
    Abstract: An ALUA path distribution system includes host devices coupled to storage subsystems by aggregated networking devices. A first aggregated networking device snoops communications between the host devices and the storage subsystems to identify first snooped information, retrieves second snooped information identified by a second aggregated networking device, and uses the snooped information to build a path distribution table identifying each active-optimized path provided by the aggregated networking devices between the host devices and respective LUNs on the storage subsystems.
    Type: Grant
    Filed: October 25, 2019
    Date of Patent: August 17, 2021
    Assignee: Dell Products L.P.
    Inventors: Ramesh Kumar Subbiah, Vibin Varghese
  • Patent number: 11093407
    Abstract: In a computer system having virtual machines, one or more unused bits of a guest physical address range are allocated for aliasing so that multiple virtually addressed sub-pages can be mapped to a common memory page. When one bit is allocated for aliasing, dirty bit information can be provided at a granularity that is one-half of a memory page. When M bits are allocated for aliasing, dirty bit information can be provided at a granularity that is 1/(2M)-th of a memory page.
    Type: Grant
    Filed: September 25, 2019
    Date of Patent: August 17, 2021
    Assignee: VMware, Inc.
    Inventors: Benjamin C. Serebrin, Bhavesh Mehta
  • Patent number: 11086783
    Abstract: A dynamic premigration protocol is implemented in response to a secondary tier returning to an operational state and an amount of data associated with a premigration queue of a primary tier exceeding a first threshold. The dynamic premigration protocol can comprise at least a temporary premigration throttling level. An original premigration protocol is implemented in response to an amount of data associated with the premigration queue decreasing below the first threshold.
    Type: Grant
    Filed: October 10, 2019
    Date of Patent: August 10, 2021
    Assignee: International Business Machines Corporation
    Inventors: Koichi Masuda, Katja I. Denefleh, Joseph M. Swingler
  • Patent number: 11080142
    Abstract: Methods and systems for improving data back-up, recovery, and search across different cloud-based applications, services, and platforms are described. A data management and storage system may direct compute and storage resources within a customer's cloud-based data storage account to back-up and restore data while the customer retains full control of their data. The data management and storage system may direct the compute and storage resources within the customer's cloud-based data storage account to generate and store secondary layers that are used for generating search indexes, to generate and store shared space layers and user specific layers to facilitate the deduplication of email attachments and text blocks, to perform a controlled restoration of email snapshots such that sensitive information (e.g., restricted keywords) located within stored snapshots remains protected, and to detect and preserve emails that were received or transmitted and then deleted between two consecutive snapshots.
    Type: Grant
    Filed: June 28, 2019
    Date of Patent: August 3, 2021
    Assignee: RUBRIK, INC.
    Inventors: Jihang Lim, Noel Moldvai
  • Patent number: 11061597
    Abstract: A method includes migrating data within an addressing set to a second storage unit of the DSN. The method further includes establishing a virtual storage unit within the DSN regarding the addressing set. While migrating the data within the addressing set, the method further includes processing, by the virtual storage unit, data access requests having a DSN address within the addressing set. When the migrating the data is complete, the method further includes sending a notification to the virtual storage unit that the migration is complete. The method further includes coordinating, between the virtual storage unit and the second storage unit, an update of the second storage unit regarding the data access requests processed by the virtual storage unit.
    Type: Grant
    Filed: August 28, 2018
    Date of Patent: July 13, 2021
    Assignee: Pure Storage, Inc.
    Inventor: Manish Motwani
  • Patent number: 11030109
    Abstract: A method of contention-free lookup including mapping a key of a cache lookup operation to determine an expected location of object data, walking a collision chain by determining whether a cache header signature matches a collision chain signature, when the cache header signature does not match, again walking the collision chain, when the cache header signature matches, determining whether a key in the cache header signature matches the key of the cache lookup operation, when the key does not match, reading a cache entry corresponding to the cache lookup operation, and repopulating the cache entry, when the key matches, acquiring an entry lock, and determining whether the key still matches after acquiring the entry lock, when the key still matches finding the object data in the expected location, and when the key no longer matches, releasing the entry lock, and again walking the collision chain.
    Type: Grant
    Filed: June 6, 2019
    Date of Patent: June 8, 2021
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Vijaya Jakkula, Siva Ramineni, Venkata Bhanu P. Gollapudi
  • Patent number: 11030112
    Abstract: Enhanced address space layout randomization is disclosed. For example, a memory includes first and second memory addresses of a plurality of memory addresses, where at least one of the plurality of memory addresses is a decoy address. A memory manager executes on a processors to generate a page table associated with the memory, which includes a plurality of page table entries. Each page table entry in the plurality of page table entries is flagged as in a valid state. The page table is instantiated with first and second page table entries of the plurality of page table entries associated with the first and second memory addresses respectively. A plurality of unused page table entries of the plurality of page table entries, including a decoy page table entry, is associated with a decoy address.
    Type: Grant
    Filed: May 25, 2018
    Date of Patent: June 8, 2021
    Assignee: Red Hat, Inc.
    Inventor: Michael Tsirkin
  • Patent number: 11016665
    Abstract: A data storage device that includes data storage media, with at least one of the data storage media having a plurality of embedded firmware modules. The data storage media include a non-volatile memory having different usage modes, with each different usage mode being associated with a different status of the data storage device, and each of the different usage modes having different space allocation configurations for data generated by the plurality of embedded firmware modules. A controller communicatively coupled to the non-volatile memory. The controller determines a change in the status of the data storage device and, in response to the change in the status of the data storage device, dynamically alters the usage mode of the non-volatile memory from a first one of the usage modes to a second one of the usage modes.
    Type: Grant
    Filed: January 23, 2018
    Date of Patent: May 25, 2021
    Assignee: SEAGATE TECHNOLOGY LLC
    Inventors: Abhay T. Kataria, Amruta Rameshchandra Inamdar
  • Patent number: 11010054
    Abstract: According to one embodiment, a data processing system includes a plurality of processing units, each processing unit having one or more processor cores. The system further includes a plurality of memory roots, each memory root being associated with one of the processing units. Each memory root includes one or more branches and a plurality of memory leaves to store data. Each of the branches is associated with one or more of the memory leaves and to provide access to the data stored therein. The system further includes a memory fabric coupled to each of the branches of each memory root to allow each branch to access data stored in any of the memory leaves associated with any one of remaining branches.
    Type: Grant
    Filed: June 10, 2016
    Date of Patent: May 18, 2021
    Assignee: EMC IP HOLDING COMPANY LLC
    Inventors: Mark Himelstein, Bruce Wilford, Richard Van Gaasbeck, Todd Wilde, Rick Carlson, Vikram Venkataraghavan, Vishwas Durai, James Yarbrough, Blair Barnett