Patents Examined by Gautam Sain
  • Patent number: 11016665
    Abstract: A data storage device that includes data storage media, with at least one of the data storage media having a plurality of embedded firmware modules. The data storage media include a non-volatile memory having different usage modes, with each different usage mode being associated with a different status of the data storage device, and each of the different usage modes having different space allocation configurations for data generated by the plurality of embedded firmware modules. A controller communicatively coupled to the non-volatile memory. The controller determines a change in the status of the data storage device and, in response to the change in the status of the data storage device, dynamically alters the usage mode of the non-volatile memory from a first one of the usage modes to a second one of the usage modes.
    Type: Grant
    Filed: January 23, 2018
    Date of Patent: May 25, 2021
    Assignee: SEAGATE TECHNOLOGY LLC
    Inventors: Abhay T. Kataria, Amruta Rameshchandra Inamdar
  • Patent number: 11010054
    Abstract: According to one embodiment, a data processing system includes a plurality of processing units, each processing unit having one or more processor cores. The system further includes a plurality of memory roots, each memory root being associated with one of the processing units. Each memory root includes one or more branches and a plurality of memory leaves to store data. Each of the branches is associated with one or more of the memory leaves and to provide access to the data stored therein. The system further includes a memory fabric coupled to each of the branches of each memory root to allow each branch to access data stored in any of the memory leaves associated with any one of remaining branches.
    Type: Grant
    Filed: June 10, 2016
    Date of Patent: May 18, 2021
    Assignee: EMC IP HOLDING COMPANY LLC
    Inventors: Mark Himelstein, Bruce Wilford, Richard Van Gaasbeck, Todd Wilde, Rick Carlson, Vikram Venkataraghavan, Vishwas Durai, James Yarbrough, Blair Barnett
  • Patent number: 10997087
    Abstract: A system includes a direct memory access controller and a memory coupled to the direct memory access controller. The memory stores a linked list of records. Each record contains a first field determining the number of fields of a next record. For example, each record can be representative of parameters of execution of a data transfer by the direct memory access controller.
    Type: Grant
    Filed: July 15, 2019
    Date of Patent: May 4, 2021
    Assignee: STMICROELECTRONICS (GRENOBLE 2) SAS
    Inventor: François Cloute
  • Patent number: 10983792
    Abstract: A memory device performing an internal copy operation is provided. The memory device may receive a source address, a destination address, and page size information together with an internal copy command, compares the source address with the destination address, and performs an internal copy operation. The internal copy operation may be an internal block copy operation, an inter-bank copy operation, or an internal bank copy operation. The internal copy operation may be performed with respect to one-page data, half-page data, or quarter-page data, based on the page size information. The memory device may output as a flag signal a copy-done signal indicating that the internal copy operation has been completed.
    Type: Grant
    Filed: November 13, 2018
    Date of Patent: April 20, 2021
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Young-soo Sohn, Sei-jin Kim, Kwang-il Park, Tae-young Kim, Chul-woo Park
  • Patent number: 10970240
    Abstract: Apparatus and methods for operation of a memory controller, memory device and system are described. During operation, the memory controller transmits a read command which specifies that a memory device output data accessed from a memory core. This read command contains information which specifies whether the memory device is to commence outputting of a timing reference signal prior to commencing outputting of the data. The memory controller receives the timing reference signal if the information specified that the memory device output the timing reference signal. The memory controller subsequently samples the data output from the memory device based on information provided by the timing reference signal output from the memory device.
    Type: Grant
    Filed: May 7, 2019
    Date of Patent: April 6, 2021
    Assignee: Rambus Inc.
    Inventors: Ian Shaeffer, Thomas J. Giovannini
  • Patent number: 10949103
    Abstract: Techniques to satisfy quality of service (QoS) requirements on a per virtual machine basis natively in a storage system are disclosed. In various embodiments, for each of a plurality of virtual machines a corresponding input/output (I/O) request queue is stored on the storage system. Requests are scheduled to be pulled from the respective request queues and added to a corresponding storage operation pipeline at the storage system in an order determined based at least in part on a per virtual machine quality of service parameter.
    Type: Grant
    Filed: April 24, 2019
    Date of Patent: March 16, 2021
    Assignee: Tintri by DDN, Inc.
    Inventors: Sumedh V. Sakdeo, Edward K. Lee, Brandon W. Salmon
  • Patent number: 10909087
    Abstract: A computer-implemented method according to one embodiment includes creating journal entries in response to performing predetermined operations on a sequential storage medium, storing the journal entries in a memory in response to creation thereof for creating an operation journal, and upon occurrence of a predefined event, saving the operation journal. A computer program product according to another embodiment includes a computer readable storage medium having program instructions embodied therewith. The computer readable storage medium is not a transitory signal per se. The program instructions are readable and/or executable by a controller to cause the controller to perform a method including creating, by the controller, journal entries in response to performing predetermined operations on a sequential storage medium. The journal entries are stored, by the controller, in a memory in response to creation thereof for creating an operation journal.
    Type: Grant
    Filed: January 23, 2018
    Date of Patent: February 2, 2021
    Assignee: International Business Machines Corporation
    Inventors: Atsushi Abe, Eiji Tosaka
  • Patent number: 10871914
    Abstract: A memory management method, a memory storage device and a memory control circuit unit are provided. The method includes: storing first data to a first physical erasing unit and marking the first physical erasing unit as belonging to a first group, wherein the first data belongs to a first type; storing second data to a second physical erasing unit and marking the second physical erasing unit as belonging to a second group, wherein the second data belongs to a second type which is different from the first type; selecting a third physical erasing unit as an active physical erasing unit and marking the third physical erasing unit as belonging to the first group; when a data moving operation is performed, moving valid data of the first physical erasing unit to the third physical erasing unit according to a first parameter of the first physical erasing unit.
    Type: Grant
    Filed: February 18, 2019
    Date of Patent: December 22, 2020
    Assignee: PHISON ELECTRONICS CORP.
    Inventors: Ping-Chuan Lin, Shii-Yeu Chern, Tai-Yuan Huang, Yi-Hsuan Lin, Chi-Shun Kao
  • Patent number: 10860214
    Abstract: The various embodiments described herein include methods, devices, and systems for processing memory operation requests. In one aspect, a method is performed at a computing system having one or more processors and non-volatile memory: (1) obtaining a plurality of internal memory operation requests for the non-volatile memory, the plurality of internal memory operation requests originating from within the computing system; (2) obtaining a plurality of external memory operation requests for the non-volatile memory, the plurality of external memory operation requests originating from one or more devices remote and distinct from the computing system; and (3) regulating a rate at which the plurality of internal memory operation requests are transferred to the non-volatile memory based on an amount of external memory operation requests in the plurality of external memory requests.
    Type: Grant
    Filed: November 17, 2017
    Date of Patent: December 8, 2020
    Assignee: STORMAGIC LIMITED
    Inventor: Christopher J. Farey
  • Patent number: 10846220
    Abstract: A memory system may include: a memory device having a plurality of banks, each comprising a memory cell region including a plurality of memory cells, and a page buffer unit; and a controller suitable for receiving a write address and write data from a host, and controlling a write operation of the memory device, wherein the controller comprises: a page buffer table (PBT) comprising fields to retain the same data as the page buffer units of the respective banks; and a processor suitable for comparing the write data to data stored in a field of the PBT, corresponding to the write address, and controlling the memory device to write the write data or the data stored in the page buffer unit to memory cells selected according to the write address, based on a comparison result.
    Type: Grant
    Filed: January 18, 2018
    Date of Patent: November 24, 2020
    Assignee: SK hynix Inc.
    Inventors: Seung-Gyu Jeong, Dong-Gun Kim, Do-Sun Hong
  • Patent number: 10838643
    Abstract: A technique for managing cache in a storage system that supports data deduplication renders each of a set of data blocks as multiple sub-blocks and loads a cache-resident digest database on a per-block basis, selectively creating new digest entries in the database for all sub-blocks in a block, but only for blocks that contain no duplicate sub-blocks. Sub-blocks of blocks containing duplicates are excluded. By limiting digest entries to sub-blocks of blocks that contain no duplicates, the storage system limits the size of the digest database, and thus of the cache, while also biasing the contents of the digest database toward entries that are likely to produce deduplication matches in the future.
    Type: Grant
    Filed: October 31, 2018
    Date of Patent: November 17, 2020
    Assignee: EMC IP Holding Company LLC
    Inventors: Sorin Faibish, Philippe Armangau, Istvan Gonczi, Ivan Bassov, Vamsi K. Vankamamidi
  • Patent number: 10831651
    Abstract: A computer program product, according to one embodiment, includes a computer readable storage medium having program instructions embodied therewith. The computer readable storage medium is not a transitory signal per se. Moreover, the program instructions are readable and/or executable by a controller to cause the controller to perform a method which includes: assigning data having a first heat to a first data stream, assigning data having a second heat to a second data stream, and writing the data streams simultaneously, in parallel, to page-stripes having a same index across a series of planes of memory. The writing of the first data stream begins at an opposite end of the series of planes as the writing of the second data stream, the writing of the streams being toward one another. Other systems, methods, and computer program products are described in additional embodiments.
    Type: Grant
    Filed: June 27, 2018
    Date of Patent: November 10, 2020
    Assignee: International Business Machines Corporation
    Inventors: Charles J. Camp, Timothy J. Fisher, Aaron D. Fry, Nikolas Ioannou, Ioannis Koltsidas, Roman A. Pletka, Sasa Tomic
  • Patent number: 10802973
    Abstract: An apparatus includes a first database, a memory, and first and second processors. The first database stores a list including a first identifier assigned to the first processor and a second identifier assigned to the second processor. The processors each randomly shuffle a copy of the list and place the first element of their shuffled copy in a third list. Each processor further determines that the first identifier appears a first number of times and the second identifier appears a second number of times in the third list, the first number greater than the second number. In response to determining that the first number is greater than the second number, the first processor copies data stored in a second database into the memory and sets a flag to true, while the second processor determines that the flag is set to true and accesses the data copy stored in the memory.
    Type: Grant
    Filed: July 1, 2019
    Date of Patent: October 13, 2020
    Assignee: Bank of America Corporation
    Inventors: Udaya Kumar Raju Ratnakaram, Niroop Reddy Patimeedi, Sarvari Tadimalla, Maruthi Shanmugam, Jian Jim Chen, Punit Srivastava
  • Patent number: 10795827
    Abstract: Storage devices that can perform adaptive management of intermediate storage memory, and methods for use therewith, are described herein. Such a storage device includes non-volatile memory, wherein a portion thereof is designated as intermediate storage (IS) memory and another portion thereof designated as main storage (MS) memory. The IS memory has lower write and read latencies, greater endurance, and lower storage density and capacity than the MS memory. In certain embodiments, a host activity pattern is predicted, a relocation schemes is selected based on the predicted host activity pattern, and the selected relocation scheme is executed to thereby selectively relocate one or more portions of the data from the IS memory to the MS memory in accordance with the selected relocation scheme. The relocation scheme that is selected and executed can change over time. Additionally relocation schemes can be generated based on activity log(s) and thereafter selected for execution.
    Type: Grant
    Filed: November 17, 2017
    Date of Patent: October 6, 2020
    Assignee: Western Digital Technologies, Inc.
    Inventors: Judah Gamliel Hahn, Alexander Bazarsky, Shay Benisty, Ariel Navon
  • Patent number: 10768845
    Abstract: A storage device includes a storage retaining content data, an input receiving instructions to reproduce the content data stored in the storage and a reproducer outputting the content data to an external reproducing device. The storage retains a table including identification information of the external reproducing device and a data format of the content data reproducible in the external reproducing device. The reproducer includes a notifier notifying reproduction information necessary for the external reproducing device to reproduce the content data before the content data are outputted to the external reproducing device in response to a reproduction instruction, and a data controller acquiring unique identification information for the external reproducing device when the external reproducing device is connected to the storage device and converting the content data into the data format reproducible in the external reproducing device and outputting the content data thereto.
    Type: Grant
    Filed: January 23, 2018
    Date of Patent: September 8, 2020
    Assignee: BUFFALO, INC.
    Inventor: Naoki Matsumoto
  • Patent number: 10768965
    Abstract: Systems and methods are provided to reduce the number of redundant copy operations performed as part of a live migration of a virtual machine executing a guest. A hypervisor can queue the copy operations in a processing engine. While pre-copying for the live migration of the VM, the guest may continue to write to the pages. In one embodiment, the processing engine may clear a dirty page just before performing the copy operation of the modified page to a target device, thus extending the window of time to capture any future writes to that page.
    Type: Grant
    Filed: May 2, 2018
    Date of Patent: September 8, 2020
    Assignee: Amazon Technologies, Inc.
    Inventors: Adi Habusha, Ali Ghassan Saidi
  • Patent number: 10761741
    Abstract: A computer-implemented method and system for managing and sharing data using smart pointers. The computer-implemented method includes obtaining original data and storing the original data in memory. Further, the computer-implemented method includes creating a smart pointer for the original data in a first thread. Furthermore, the computer-implemented method includes duplicating the smart pointer from the first thread to a second thread. Moreover, the computer-implemented method includes share the original data across the first thread and the second thread.
    Type: Grant
    Filed: April 7, 2016
    Date of Patent: September 1, 2020
    Assignee: Beijing Baidu Netcome Science and Technology Co., LTD.
    Inventor: Yingze Bao
  • Patent number: 10754653
    Abstract: A system for translating compressed instructions to instructions in an executable format is described. A translation unit is configured to decompress compressed instructions into a native instruction format using X and Y indices accessed from a memory, a translation memory, and a program specified mix mask. A level 1 cache is configured to store the native instruction format for each compressed instruction. The memory may be configured as a paged instruction cache to store pages of compressed instructions intermixed with pages of uncompressed instructions. Methods of determining a mix mask for efficiently translating compressed instructions is also described. A genetic method uses pairs of mix masks as genes from a seed population of mix masks that are bred and may be mutated to produce pairs of offspring mix masks to update the seed population. A mix mask for efficiently translating compressed instructions is determined from the updated seed population.
    Type: Grant
    Filed: November 24, 2015
    Date of Patent: August 25, 2020
    Assignee: QUALCOMM Incorporated
    Inventors: Sergei Larin, Lucian Codrescu, Anshuman Das Gupta
  • Patent number: 10747451
    Abstract: Techniques to automatically allocate resources among storage system resource consumers are disclosed. In various embodiments, for each of a plurality of heterogeneous categories of resource consumer of the storage system a corresponding allocated portion of storage system resources to be available for use to perform operations associated with that category of resource consumer is determined. A storage system is configured automatically to provide access to resources of the storage system based at least in part on the respective portions of storage system resources allocated to each category of resource consumer, including by ensuring availability to workloads associated with each category at any given time at least a minimum amount of storage system resources corresponding to the portion of storage system resources allocated to that category.
    Type: Grant
    Filed: February 14, 2019
    Date of Patent: August 18, 2020
    Assignee: Tintri by DDN, Inc.
    Inventors: Sumedh V. Sakdeo, Edward K. Lee, Brandon W. Salmon
  • Patent number: 10747675
    Abstract: Embodiments of the present disclosure generally relate to a method and device for managing caches. In particular, the method may include in response to receiving a request to write data to the cache, determining the amount of data to be written. The method may further include in response to the amount of the data exceeding a threshold amount, skipping writing data to the cache and writing the data to a lower level storage of the cache. Corresponding systems, apparatus and computer program products are also provided.
    Type: Grant
    Filed: September 20, 2017
    Date of Patent: August 18, 2020
    Assignee: EMC IP Holding Company LLC
    Inventors: Lester Zhang, Denny Dengyu Wang, Chen Gong, Geng Han, Joe Liu, Leon Zhang