Abstract: The specification discloses a solid state auto-reset circuit breaker intended for use in ac circuits, dc circuits and ac/dc circuits. A current sensing device is used to generate a voltage drop proportional to the current flowing through the device. When the voltage drop reaches a predetermined level, resulting from an over-current condition, it trips a control means that opens a solid state switch in the line. After a defined delay interval the circuit will automatically reset to close the solid state switch. If the over-current condition still exists, the control means will again open the solid state switch. This cycle is repeated at the delay interval until the over-current condition has subsided. Circuits are also disclosed which provide over-voltage protection, through detectors which trigger the control means when an over-voltage condition is detected. The application of the invention to lightning or surge protection is also disclosed, for single line and multiline environments.

Abstract: An on-board oil quality sensor for use in an internal combustion engine formed of a pair of resisitve elements mounted on a common substrate, wherein one of the resistive elements is exposed to the oil for corrosion as the oil contaminants increase and the other resistive element is protectively sealed from the oil contaminants. Both resistive elements are exposed to the oil temperature and are suitable for monitoring by a bridge type circuit to determine the level of corrosive contaminants in the oil.

Abstract: The encoder is particularly for ultra fast high resolution flash analog-to-digital converters. A simple multiplexing is performed. An optional buffer memory stores selected codes prior to a final processing which can be relatively slow. An input register is unnecessary. The input code is divided into a least significant section code and at least one more significant section code each having a least significant bit. A multiplexer selects the least significant section code or a portion of one of the more significant section codes excluding the least significant bit thereof, in response to the least significant bits. The multiplexer includes a plurality of buffers for separately receiving the section codes and having outputs coupled in parallel. A decoder converts the least significant bits and selected code into the binary output code.

Abstract: An arc preventing electrostatic power supply suitable for operating an electrostatic paint atomizer such as a rotary atomizer. High voltage control is based on the high voltage current, as measured in the ground return path. The power supply is controlled to provide a substantially constant high voltage DC output up to a predetermined current and an output voltage which rapidly drops off as the current increases above the predetermined current. The magnitude of an AC component superimposed on the high voltage DC current is detected to determine incipient arcing. Upon detecting an incipient arcing condition, the output voltage is interrupted for a predetermined short time. When the output voltage is turned back on, it is ramped up from a low level back to the normal high voltage level. While the output voltage is less than a predetermined low level, the sensitivity of the incipient arc detection circuit is increased.

Abstract: A full search block matching algorithm includes a charge-domain serial tapped delay line as an input buffer, and an array of charge domain signal processors. The delay line shifts and holds analog sampled data which are in the form of charge packets. At each stage of delay, the signals are nondestructively sensed and coupled to a corresponding signal processor, and the sampled data are transferred and subsequently processed in parallel. The processed data from all the processors can be read out either in a parallel or serial format through a parallel-in-serial-out output buffer. In this structure, only the serial input buffer has to be clocked at the system throughout rate; the internal clock rate of each processor is reduced by the number of parallel processors. Within each processor, all of the computation functions are performed in the charge domain, and local charge domain memories are included for storing the processed signal.

Abstract: A successive approximation analog to digital converter is provided with a variable reference voltage. A comparator compares an analog input voltage and an analog comparison voltage to obtain a digital output signal. Before the analog comparison voltage becomes lower than the analog input voltage, the first time after the analog to digital conversion starts, the second digital signal is changed in response to a first clock signal to decrease the reference voltage so that the first digital signal output form the first register is not changed. After the analog comparison voltage becomes lower than the analog input voltage the first time after the analog to digital conversion starts, the second digital signal is not changed so that the reference voltage is kept constant. The first digital signal is then changed in response to a second clock signal and the digital output signal to change the analog comparison voltage, whereby the bit member of the digital-to-analog converter is reduced.

Abstract: An apparatus for converting an analog image signal to a digital image signal based on a reference voltage, includes a counter having a control terminal, for counting a first signal and outputting a counted value in digital form, a D/A converter for converting the counted value to an analog voltage signal served as the reference voltage, an A/D converter for converting the analog image signal to the digital image signal based on the reference voltage generated by the D/A converter, and a comparator for comparing in magnitude the digital image signal and a threshold level used for limiting the magnitude of the digital image signal, thereby outputting a control signal based on the results of comparison. The counter continues to count the first signal until the control signal derived from the comparator is supplied to the control terminal of the counter.

Abstract: A PWM digital-to-analog converter is disclosed in which a value representing a differential between a first pulse width modulated waveform based upon input digital data and a second pulse width modulated waveform representing a 2's complement version of the input digital data is produced by a differential amplifier and high frequency components thereof are attenuated to produce an analog output signal and with an improved distortion factor.

Abstract: A digital-to-analog converter converts digital data in the floating-point representation into an analog signal. The mantissa part of the digital data is first converted into a first analog signal by an R-2R resistor ladder network. The first analog signal thus obtained is directly supplied to another r-2r resistor ladder network to produce second analog signals whose values are 2.sup.-N (N=0, 1, 2, . . . ) magnifications of the first analog signal. And, one of the second analog signals is selectively outputted in accordance with the exponent part of the digital data. A data converter is also provided for converting digital data in the form of a fix-point number into floating point data.

Abstract: A signal source arrangement includes a group of signal sources calibrated so that each signal source produces an identical unit signal. The unit signals are combined to form the output signal. Each signal source also produces a similar undesirable spurious signal caused by the calibration procedure. The combination sequence or the calibration sequence is arranged so as to minimize the undesirable effect of the resulting spurious signals in the combined output signal.

Abstract: A DAC embodied in a CMOS integrated circuit converts a multi-bit digital signal to an analog-current signal. A higher-order portion of the digital signal, e.g., the most significant 5 bits of a byte, are decoded separately from the lower-order portion, e.g., the 3 least significant bits. The DAC includes circuitry for producing a first bias voltage, a first set of current sources each biased by the first bias voltage to produce a switchable current having a unit magnitude, and switching circuitry controlled by the decoded lower-order portion to cause a selected number of the unit-magnitude currents to contribute to the analog-current signal.

Abstract: A serial-to-parallel analog CCD GaAs device provides high speed A/D or D/A conversion. A high speed analog signal is sampled by shifting the analog data serially into "n" CCD elements. Then a parallel load pulse transfers the analog data into multiple CCD holding elements. A bank of A/D converters converts the analog data. Conversely, the outputs of a bank of D/A converters are loaded in parallel into a serial CCD device of "n" elements. The serial CCD device is shifted out serially to complete the conversion to an analog signal.

Abstract: A fast, high-resolution A/D converter circuit includes a combination of a main-range up/down counter and a subrange A/D converter. An output from the up/down counter for upper bits is D/A-converted and subtracted from an input signal, and the remainder of subtraction is A/D-converted by the subrange A/D converter, thereby obtaining high-resolution conversion data. The circuit has a feedback loop which detects that the remainder becomes less than LSB of the up/down counter and stops a count operation. By discriminating that the remainder is more/less a predetermined level set higher than the LSB of the counter or outside/inside a predetermined range, a count rate is switched between high and low rates. The remainder enters subrange via the low rate count stage.

Abstract: A digital-to-analog converter comprising a set of identical DAC cells each including: (1) a PNP bipolar current source transistor producing a continuous output current (equal values for all DAC cells), (2) a pair of PMOS switches connected to the collector of the bipolar transistor to divert the output current to either a ground line or a corresponding node of an R/2R ladder, (3) ladder circuitry for maintaining the full-scale ladder voltage below a predetermined level which keeps the PMOS switches in the saturated region of their characteristics, and (4) make-before-break switch control circuitry to close the PMOS switch being activated prior to opening the other PMOS switch.

Abstract: A PWM type D/A converter having a first PWM converter, a second PWM converter and an analog adder. The digital input signals are designated as odd and even numbered input signals and the reference timing points for outputting odd/even numbered input signal are designated as odd/even numbered reference timing points. The first PWM converter receive the digital input signal to output signal whose rising/falling timing point is set at the earlier/later timing, the larger the value of the odd/even numbered input signal relative to the odd/even numbered reference timing point and the pulse width is determined by the values of the odd numbered input signal and the next even numbered input signal.

Abstract: The converter incorporates a transversal filter. The filter delays are implemented in digital form prior to conversion into analog signals (preferably using switched capacitor techniques). One form of switched capacitor converter (with or without filtering) employs a single capacitor, common to a plurality of bits, appropriate weighting of the bits being achieved by controlling the switching.

Abstract: This invention discloses an analog-to-digital converter. Current supply paths are branched at the current supply terminals from the other current paths so as to be connected exclusively to the analog voltage comparator. And a circuit block of the analog voltage comparator is positioned closer to the current supply terminals than the other circuit block of DA converter, sequential comparison register, etc.

Abstract: A data acquisition for use in a high-speed data bus interface is provided with an analog acquisition circuit having analog inputs, digital outputs, a load terminal, an end-of-conversion terminal, a strobe terminal, a multiplex address output and a channel select input. A static random access memory receives data produced at the digital output of the analog acquisition circuit and stores it in addresses corresponding to the multiplexed address outputs of the analog acquisition circuit. A simple logic control circuit having an AND gate, an OR gate and a one shot circuit is connected to control the operation of the analog acquisition to provide self-starting and free running operation with synchronous turn on and turn off to prevent data contamination when the circuit is stopped.

Abstract: An apparatus adaptable for use in effecting communications between an analog device and a digital device, having an analog-digital-analog circuit for converting incoming analog signals received from the analog device to incoming digital signals, and for converting interpolated outgoing digital signals to outgoing analog signals. The analog-digital-analog device includes a single digital-to-analog converter and switches for selectively configuring the analog-digital-analog circuit to effect conversion of incoming analog signals to incoming digital signals or, alternatively, to effect conversion of outgoing digital signals to outgoing analog signals.

Abstract: A circuit that compensates for threshold voltage variations in a large array of deposited thin film MOS transistors includes a threshold voltage compensation transistor for a subset of the deposited analog thin film transistors having a prescribed source to gate threshold voltage. The source electrode of the threshold voltage compensation transistor receives a voltage corresponding to the maximum threshold voltage in the large array. The gate and drain electrodes of the threshold voltage compensation transistor are connected together and to one terminal of a capacitor. The other terminal of the capacitor is connected to a second voltage and the capacitor is momentarily discharged to set the threshold voltage compensation transistor gate and drain electrodes to the second voltage. The gate and drain electrodes of the threshold voltage compensation transistor are connected to the gate electrodes of the subset of analog thin film transistors.