Abstract: A digital/analog converting device comprises a first digital/analog converter for converting upper M bits of an input digital signal into a first analog signal; a memory for receiving, as address data, at least a digital signal of lower N bits of the input digital signal to output lower-bit-output-approximate data of S (S>N) bits in response to the address data; a second digital/analog converter for converting digital data at least including the S-bit lower-bit-output-approximate data into a second analog signal; and an analog adder for outputting an added analog signal obtained by adding the first and second analog signals at a predetermined ratio. The S-bit lower-bit-output-approximate data are set such that, supposing a level change of the added analog signal with respect to a change of an LSB of the upper M bits being .DELTA.L, a minimum step increase of the digital signal of lower N bits causes a level of the added analog signal to increase by about .DELTA.L/2.sup.N.

Abstract: An A/D (analog-to-digital) converter circuit that controls a frequency characteristic of an input video signal in response to a sampling signal of a variable frequency to reduce distortions such as a folded distortion and so on caused by the A/D conversion.

Abstract: Ultra fast high resolution digital-to-analog converter converts input code into a corresponding output current or voltage. The individual currents are continuously adjusted and coupled to an output via switches. Resistors can have two values. On-resistances of any switches and values of capacitors are insignificant. No transistor matching is necessary, wherein FETs are preferred.Current sources provide currents in a response to base signals stored in the capacitors. The resistors conduct the currents and switches couple the currents to the output in response to the input code. A reference circuit provides a reference code and reference signal corresponding thereto. A multiplexer selects a voltage appearing across one of the resistors, in response to the reference code. A comparator compares the selected voltage against reference signal and provides a corrective signal. A demultiplexer applies the corrective signal to one of the capacitors in response to the reference code.

Abstract: A sample rate conversion circuit converts first digital data processed by a first clock signal having a first frequency into digital data processed by a second clock signal having a second frequency. A ring oscillator has a predetermined number of voltage-controlled gate delay elements connected to each other in the form of a loop so as to output polyphase delay clock signals and a predetermined self-excited oscillation signal. A phase-locking circuit applies a control voltage corresponding to a phase difference between the first clock signal and the self-excited oscillation signal to each of the voltage-controlled gate delay elements so as to phase-lock the first clock signal with the self-excited oscillation signal output from the ring oscillator. A latch circuit latches the polyphase delay clock signals output from the ring oscillator in accordance with the second clock signal.

Abstract: A floating-point digital-to-analog converting system which includes a mantissa digital-to-analog converter (DAC) and an exponent DAC. Normally, the mantissa DAC has a digital-to-analog converting accuracy higher than that of the exponent DAC because of differences in their construction. Hence, as long as the accuracy of the mantissa DAC is greater than that of the exponent DAC, an analog mantissa output from the mantissa DAC is used as an analog output of the present system. On other other hand, once the accuracy of the mantissa DAC goes below that of the exponent DAC, data obtained by shifting digital input data is applied to the mantissa DAC. Then, the exponent DAC multiplies the analog mantissa by a weight corresponding to the digital exponent data included in the digital input data. Thus, an analog output is obtained from the exponent DAC.

Abstract: An electrical circuit suitable for encoding binary information, in accordance with a novel modulation method, is provided. The encoder circuit includes: a clock driver; an n-phase counter driven by the clock driver for producing a succession of event-cells, wherein each event-cell is demarcated by a pair of similar, unique clock transitions; first logic circuitry for generating a first transitional event in a first event-cell in response to a first information; and second logic circuitry for generating a second transitional event in a second event-cell in response to a second information, the first transitional event and the second transitional event differing by the number of transitions occurring per event-cell. A specific, preferred encoder circuit embodiment is set forth.

Abstract: A fully optical A/D converter is disclosed in which the difference in light intensity from two outputs of a two-arm interferometer in each channel is detected. The difference in light intensity is varied in accordance with a phase shift in the light passing through one arm of the interferometer. The phase shift is accomplished by the use of a non-linear optical material, the optical properties of which are altered based on the characteristics of an input optical signal to be digitized. Thus, the difference in light intensity corresponds to the magnitude of the input optical signal.

Abstract: A current sense circuit (100) includes a semiconductor power switch such as a MOSFET (102) having a source metallization contact pad (14) with a conductor jumper bond wire (106) directly connected thereto in the MOSFET module housing (104), which bond wire is connected to a source terminal lead frame within the module, which lead frame extends externally of the module for connection to a load (22) and load voltage (24). The current sense circuitry includes amplifier circuitry (150, 168) having first and second inputs (122, 124) connected to the source bond wire (106) at spaced points (126, 128) along the bond wire within the module housing (104) without insertion of additional series shunt resistance in the bond wire (106) between such points (126, 128), and sensing current flow through the bond wire (106) by sensing voltage between such points (126, 128) and amplifying such voltage.

Abstract: A bipolar analog voltage is converted into a digital signal by sensing the polarity of the voltage and selectively supplying a bias voltage to an analog-to-digital converter, which can preferably be a charge balanced voltage to frequency converter, as a function of the sensed polarity. The voltage to frequency converter has a double valued variable frequency output with a discontinuity at zero volt such that the converter derives a maximum output frequency for a maximum positive voltage and also for a negative value slightly displaced from zero; the voltage to the frequency converter minimum output frequency is derived from positive voltages slightly greater than zero and for maximum negative voltages. The converter output frequency and the sensed polarity are supplied to a frequency to digital converter which derives an output signal having a bit representing the polarity of the analog voltage and additional bits indicative of the magnitude of the analog voltage.

Abstract: A leakage current preventing means for a drier includes a power circuit connected to an AC source, a touch control circuit connected to the power circuit and having a touch control IC and a touch control terminal capable of actuating the touch control IC, an output circuit connected to the touch control circuit and having a control medium which can be triggered into conduction by a pulse output from the IC and controls two junctions of the fire and ground wires from the AC source for being power supplied, and a leakage current detecting circuit connected to the touch control circuit and including a sensor for detecting an impedance change in the drier and an actuating medium capable of being energized into conduction in response to the impedance change to enable that the IC has no voltage output which results in non-conduction of the control medium which in turn results in no possible leakage current between the two junctions.

Abstract: An adaptive single-bit encoder and decoder has its adaptive function determined by dynamically dividing the message frequency band into delta-sigma and delta modulation regimes of operation. In a practical embodiment this is accomplished by varying the corner frequency of a variable-frequency low-pass filter in a leaky integrator so that below the corner frequency the operation is that of delta-sigma modulation and above the corner frequency the operation is that of delta modulation. An adaptation control circuit removes the clock signal component from the encoded bit stream to provide an analog signal representative of bit stream information or loading for use in generating the control signal. The analog signal is peak rectified, smoothed, and (optionally) non-linearly processed to provide the control signal.

Abstract: An apparatus for controlling the intensity and on/off status of an incandescent light bulb as a function of the proximity of an object to a sensing plate. The frequency of a signal is varied from a nominal value when the presence of the object is sensed. A pulse is generated having a duration proportional to the time over which the signal if varied from its nominal frequency. The duration of the generated pulse, in relation to a pulse of predetermined width, is used to control a gated oscillator. The output of the gated oscillator is counted. The count obtained is used to control the operation of a TRIAC, which in turn connects power to the incandescent bulb.

Abstract: The adaptive data compression apparatus is located within a tape drive control unit which is interposed between one or more host computers and one or more tape transports. The adaptive data compression apparatus functions to efficiently compress a user data file received from a host computer into a bit oriented compressed format for storage on the magnetic tape that is loaded in the tape transport. The data compression apparatus divides each block of an incoming user data file into predetermined sized segments, each of which is compressed independently without reference to any other segment in the user data file. The data compression apparatus concurrently uses a plurality of data compression algorithms to adapt the data compression operation to the particular data stored in the user data file. A cyclic redundancy check circuit is used to compute a predetermined length CRC code from all of the incoming user data bytes before they are compressed.

Abstract: A plurality of equally spaced terminals may be disposed at a side edge of a substantially uniformly resistive thin film. A reference potential (e.g. ground) may be applied to the second side of the film. An energizing voltage may be applied at the juncture between the first side edge and a particular one of the top and bottom edges of the film. In this way, the successive terminals receive voltages with a logarithmic relationship relative to the terminal positions. When a linear relationship of voltages is desired at successive terminals in a low range, no reference potential is applied to the second side edge of the thin film. Instead, the other one of the top and bottom edges may receive the reference voltage. Alternatively no reference voltage may be applied and terminals indicating the linear voltages may be disposed at such other edge.

Abstract: An ESD protection circuit, suitable for use as part of an integrated circuit, limits the voltage potential at the contacts of the integrated circuit to a voltage potential difference range relative to, though extending beyond the voltage source potentials of the circuit protected. The ESD protection is effective regardless of whether the integrated circuit is powered. The ESD protection circuit includes a clamp subcircuit for limiting the voltage potential at a clamp point to a first voltage range approximately defined by the voltage source potentials and a voltage offset subcircuit, coupled between the clamp point and an integrated circuit contact, to establish a second voltage range encompassing the first voltage range. The voltage offset subcircuit conducts current between the clamp point and the contact to limit the voltage potential at the contact to the second voltage range.

Abstract: A decoder is capable of decoding on a maximum likelihood basis coded symbols of requivalently high coding rate which are produced by deleting those code bits which are located at particular positions in a time sequence of convolutional symbols of low coding rate. The decoder includes a serial-to-parallel (SP) converter for converting a serial data sequence from a dummy bit inserter into parallel sequences. The frequency division phase of the SP converter is determined by a second timing signal which the dummy bit inserter produces in synchronism with a dummy bit inserted phase. A code synchronization is established, frequency division phase synchronization is automatically established. This eliminates the need for the repetitive trial for frequency division phase synchronization only and thereby reduces a synchronization capture time.

Abstract: Electrical circuits suitable for encoding a binary data stream into a tri-bit code format. The circuits are particularly valuable for situations where the encoding or information transfer rate is dependent on unpredicable and variable transfer rate velocities and accelerations. The circuits provide "self-clocking", which, in turn, permit velocity insensitive encoding.

Abstract: An autocalibrated multistage analog to digital converter precisely maintains appropriate error correction levels for each stage during operation of the converter to minimize quantization errors. An error signal is derived from the digital output of the converter based upon the slope of the input analog signal, determined either explicitly via hardware or implicitly via software, and an overflow/underflow condition. The error signal is fed back to a calibration control circuit to generate individual error correction levels for various variable correction devices within the analog to digital converter, such as a variable analog delay device. The variations from nominal established at calibration that are due to age, temperature or other environmental factors generate the error signal that varies from a nominal value and is fed back to alter the various error correction levels to minimize the error variation.

Abstract: A sensor for sensing and quantifying the conformity of a workpiece surface contour to a predetermined design contour. The sensor consists of an array of capacitor elements on a surface having the negative image of the predetermined design contour, against which the workpiece is mated. In operation, each of the capacitor elements and the workpiece are connected to a corresponding oscillator circuit so that the frequency of each circuit is a function of the capacitance between the individual plate element and the workpiece, while the capacitance is a function of the distance between the individual plate element and the workpiece. Hence the overall output of the circuits is a function of the conformity of the workpiece surface contour to the contour or topology of the sensor surface.

Abstract: A serial-to-parallel analog CCD GaAs device provides high speed A/D or D/A conversion. A high speed analog signal is sampled by shifting the analog data serially into "n" CCD elements. Then a parallel load pulse transfers the analog data into multiple CCD holding elements. A bank of A/D converters converts the analog data. Conversely, the outputs of a bank of D/A converters are loaded in parallel into a serial CCD device of "n" elements. The serial CCD device is shifted out serially to complete the conversion to an analog signal.