Abstract: An apparatus adaptable for use with an analog-digital conversion device for effecting communications between an analog device and a digital device, the analog-digital conversion device converting incoming analog signals received from the analog device to incoming digital signals. The apparatus has a digital signal processing circuit for decimating the incoming digital signals and providing a decimated incoming digital signal to the digital device.The digital signal processing circuit is comprised of a plurality of modules which are configured so that a specified set of the plurality of modules effects a specified number of iterations of decimation. The modules are further designed so that additional modules may be added to the specified set of modules to increase the iterations of decimation.

Abstract: An image signal binarization system for documents containing a mixture of two level and multiple level tone areas, such as characters and photographs, would provide an improved output if the system could distinguish between the two areas and respond accordingly. The proposed system distinguishes between the two types of areas by examining the density of a target point in relation to the average density of the surrounding points. If the density of the target point falls within a predetermined range the area is determined to be a multi-tone section otherwise the area is determined to be a two-tone section. The binarization system upon determining a given section to be a two tone section forces the output to one or zero. For a multi-tone section the output is based upon the mean density.

Abstract: An apparatus adaptable for use with an analog-digital-analog conversion device for effecting communications between an analog device and a digital device, the analog-digital-analog conversion device converting incoming analog signals received from the analog device to incoming digital signals, and for converting interpolated outgoing digital signals to outgoing analog signals. The apparatus has a digital signal processing circuit for decimating the incoming digital signals and providing a decimated incoming digital signal to the digital device, and for interpolating outgoing digital signals received from the digital device and providing an interpolated outgoing digital signal to the analog-digital-analog device.The digital signal processing circuit is comprised of a plurality of modules which are configured so that a specified set of the plurality of modules effects a specified number of iterations of decimation and a specified number of iterations of interpolation.

Abstract: Errors in a sampled data process are discerned statistically throughout the process, permitting their efficient removal. An exemplary application is a subranging analog-to-digital converter (ADC), in which errors associated with component digital-to-analog (DAC) current sources are discerned and corrected automatically during the circuit's normal operation. This is achieved by continually introducing a random signal into the process, statistically examining the DAC output signal to discern error terms, and correlating the occurrences of these errors with the values of the random signal applied to the DACs so as to identify the current sources to which the error terms are due. The resulting ADC output signal is compensated to remove the random signal and is further compensated to remove the DAC error terms discerned by this statistical analysis.

Abstract: A delta-sigma modulation analog to digital converter for converting an analog input signal to a digital output signal.

Abstract: An apparatus adaptable for use in effecting communications between an analog device and a digital device, having an analog-digital-analog circuit for converting incoming analog signals received from the analog device to incoming digital signals, and for converting interpolated outgoing digital signals to outgoing analog signals. The apparatus further has a digital signal processing circuit for decimating the incoming digital signals and providing a decimated incoming digital signal to the digital device, and for interpolating outgoing digital signals received from the digital device and providing an interpolated outgoing digital signal to the analog-digital-analog device. The analog-digital-analog device includes a single digital-to-analog converter and switches for selectively configuring the analog-digital-analog circuit to effect conversion of incoming analog signals to incoming digital signals or, alternatively, to effect conversion of interpolated outgoing digital signals to outgoing analog signals.

Abstract: A delta sigma modulator arrangement in which non-ideal characteristics such as noise or offsets in amplifiers or other circuits of the circuits of the arrangement are compensated by chopper stabilisation.

Abstract: A converter for producing the function V.sub.out =V.sub.bias =V.sub.swing (1-2D), in which a DAC is combined with an operational amplifier and (typically) three or four resistors. A function of the voltage V.sub.swing, or a current corresponding thereto, is applied to the reference voltage input terminal of the DAC. The variable D is the DAC's digital input code, expressed as a decimal or fraction in the range between 0 and 1. The DAC output provides a suitably scaled and signed signal which is added to or subtracted from the offset signal V.sub.bias to produce V.sub.out.

Abstract: An improved method of generating a compressed representation of a source data string, each symbol of which is taken from a finite set of m+1 symbols, a.sub.o to a.sub.m. The method is based on an arithmetic coding procedure wherein the source data string is recursively generated as successive subintervals within a predetermined interval. The width of each subinterval is theoretically equal to the width of the previous subinterval multiplied by the probability of the current symbol. The improvement derives from approximating the width of the previous subinterval so that the approximation can be achieved by a single SHIFT and ADD operation using a suitable shift register.

Abstract: The improved data compression system concurrently processes both strings of repeated characters and textual substitution of input character strings. In this system, the performance of data compression techniques based on textual substitution are improved by the use of a compact representation for identifying instances in which a character in the input data stream is repeated. This is accomplished by nesting a run length encoding system in the textual substitution system. This structure adds the recognition of runs of a repeated character before the processor performs the textual substituted data compression operation. A further performance improvement is obtained by expanding the alphabet of symbols stored in the compressor's dictionary to include both the characters of the input data stream and repeat counts which indicate the repetition of a character.

Abstract: A digital modulation method for modulating 8-bit digital data into 14-bit digital modulation codes. The number of consecutive identical bits in a series of 14-bit digital modulation codes is restricted to 2-7. The absolute value of DSV at the end of each 14-bit digital modulation code is restricted to 2 or less, and the absolute value of DSV at each bit of any 14-bit digital modulation codes is limited to 7 or less. The direct current component of the 14-bit modulation codes can be effectively reduced.

Abstract: A high-speed universal scaler operates in real time, accepting as an input an N-bit binary data word which is to be scaled (multiplied) by a scale factor specified in units per bit. The input data word is divided into M-bit sections which are provided (together with a count value indicating the position of the M-bit section within the input data word and a scale indicator value specifying which of a plurality of programmed scale factors values is to be used) sequentially as scaling addresses specifying binary coded decimal scale data in a scale memory. The sequential outputs of the scale memory in response to the scaling addresses are summed. When the sequence of addresses has been completed and all of the sequential memory outputs have been summed, the resulting sum will be a scaled binary coded decimal value equivalent to the input data word.

Abstract: Aperture delay and jitter are reduced when the sequence of operation of a charge redistribution analog to digital converter is arranged so that signal acquisition occurs in the idle time of the converter. Conversion begins by terminating the acquisition or sample phase immediately upon receipt of the start conversion command. Approximation begins directly thereafter. Upon completion of the successive approximation conversion phase and latching the result the capacitor array is discharged. The comparator offset is sampled and held and the acquisition phase is initiated and continues until receipt or occurrence of the next start conversion command.

Abstract: An integrated circuit for digitizing a dynamic waveform with a resolution that is much higher than that which is achievable under prior art methods is disclosed. A reference clock signal T.sub.r is provided as input to at least two L-type registers over a synchronous delay line (SDL). The reference clock signal is also coupled to the L ports of the L-type registers over a sample enable circuit. The incoming waveform is input in parallel to both L-type registers. The SDL generates timing pulses at intervals that are separated by T.sub.r /N, where N is the number of taps in the SDL. N corresponds to the equally spaced intervals at which the incoming waveform is sampled. The L-type register samples the incoming waveform according to control signals provided by the sample enable circuit. The control signals are required to guarantee the set-up and hold times for the flip-flops in the L-type register. Thus, the resolution of the digitized waveform is T.sub.r /N.

Abstract: An analog-to-digital converter and method which provides error correction is disclosed that eliminates the linear and quadratic error terms which arise through capacitor value dependence upon voltage.

Abstract: An A/D converting device includes an A/D converting section having a plurality of A/D converters arranged in multi-stages. The device further has a reference data generator, a correction value memory and a controller. The data generator sequentially generates pairs of a plurality of reference analog values and reference digital values. The memory is accessed using the digital output of the first stage A/D converter. The controller has a correction mode and an application mode. In the correction mode, the controller executes such a control as to supply the reference analog values to the A/D converting section and write into the memory a difference between an digital output value of a succeeding stage A/D converter and the reference digital values corresponding to the digital output value.

Abstract: One of analog input voltages applied to a plurality of analog input terminals is selected by means of analog switches connected to the respective analog input terminals and supplied to a common terminal. In this case, each of the analog switches permits selective supply of the potential of a corresponding one of the plurality of analog input terminals in response to a control signal supplied from a controller. The common terminal is connected to the positive input terminal of a comparator. The comparator compares the voltage with a digital output value from the controller which is converted into an analog voltage by means of a D/A converter. Further, the controller generates a preset control signal in an inhibition period during which supply of a voltage from the plurality of analog input terminals to the common terminal is inhibited.

Abstract: A numeric encoding method and apparatus for neural networks, encodes numeric input data into a form applicable to an input of a neural network by partitioning a binary input into N-bit input segments, each of which is replaced with a code having M adjacent logic ones and 2.sup.N -1 logic zeros, the bit position of the least significant of the M logic ones corresponding to the binary value of the input segment it replaces. The codes are concatenated to form an encoded input. A decoding method decodes an output from the neural network into a binary form by partitioning the output into output segments having 2.sup.N +M-1 bits each, each of which is replaced with an N-bit binary segment being a bracketed weighted average of the significances of logic ones present in the output segment. The binary segments are concatenated to form a decoded output.

Abstract: A serial-to-parallel analog CCD GaAs device provides high speed A/D or D/A conversion. A high speed analog signal is sampled by shifting the analog data serially into "n" CCD elements. Then a parallel load pulse transfers the analog data into multiple CCD holding elements. A bank of A/D converters converts the analog data. Conversely, the outputs of a bank of D/A converters are loaded in parallel into a serial CCD device of the "n" elements. The serial CCD device is shifted out serially to complete the conversion to an analog signal.

Abstract: The data packer receives n-bit wide parallel data words, and it outputs m-bit wide packed parallel data words, where n is a variable and may change during the operation, and m is a fixed integer. The input data words are applied to a bit shifter and therefrom to a data output circuit where they are stored until the necessary m bits are obtained. In the preferred embodiment a control circuit which comprises an adder, receives information indicating the number of valid data bits in each input word, and it provides a running sum of the number of received valid data bits. When the number of bits in an input word is equal to or greater than m, the control circuit provides a first control signal which occurs simultaneously with an m-bit wide packed parallel output word provided by the output circuit. Any number of input bits which is less than m is added to a remainder of a previous sum which is also less than m.