Patents Examined by H. L. Williams
  • Patent number: 4906923
    Abstract: Apparatus for detecting the speed of a moving object when exposed to primary magnetic flux fields and secondary external magnetic flux fields. The apparatus includes a magnetic device which generates the primary magnetic flux fields, a multi-coil device which carries induced electric currents when exposed to the primary magnetic flux field, and an error correction circuit for offsetting the effect of the magnetic flux from the external magnetic flux sources on the induced electric current. A support device is positioned between the multi-coil device and the magnetic device to allow relative movement therebetween, corresponding to the movement of the object.
    Type: Grant
    Filed: October 7, 1988
    Date of Patent: March 6, 1990
    Assignee: Kabushiki Kaisha Toshiba
    Inventor: Noboru Aoyama
  • Patent number: 4907122
    Abstract: In a relay circuit, a stationary contact of a relay is coupled to a DC voltage source and a moving contact of the relay is coupled to a load circuit. The moving contact is switched to the stationary contact in response to a rapidly rising edge of a DC voltage applied to the relay. A voltage sensor is connected to the moving contact for detecting a voltage which appears thereat. For operating the relay, a switch is closed to apply a voltage from the DC voltage source to a pulse generator. The pulse generator generates a rectangular pulse and applies it to the relay to cause it to switch the moving contact to the stationary contact. If a voltage is not detected by the voltage sensor at the moving contact after energization of the relay, the pulse generator reapplies a rectangular pulse to the relay until a voltage appears at the moving contact, whereupon the pulse generator applies a constant voltage to the relay.
    Type: Grant
    Filed: July 6, 1988
    Date of Patent: March 6, 1990
    Assignee: NEC Corporation
    Inventor: Yoshiharu Tamura
  • Patent number: 4906996
    Abstract: There is provided according to the invention a method and apparatus for eliminating or minimizing the error due to amplifier offset or drift error in an integrating dual slope analog-to-digital converter. The converter is provided with a switching and control arrangement whereby the integrating capacitor is charged for one-half of the predetermined charging time as a function of the sum of the levels of the unknown signal and the error signal. The integrating capacitor is charged for the remaining half of the predetermined time period as a function of the difference of the levels of the unknown signal and the error signal so that the capacitor reaches a level of charge which is a function of the level of the unknown signal substantially unaffected by the level of the error signal.
    Type: Grant
    Filed: December 2, 1988
    Date of Patent: March 6, 1990
    Assignee: John Fluke Mfg. Co., Inc.
    Inventor: Richard E. George
  • Patent number: 4903025
    Abstract: A signal path setting circuit for a digital recorder comprising: a digital-to-analog converter hereinafter referred to as a D/A converter to convert a digital signal into an analog signal, a first switch to supply to the D/A converter a selected signal from a plurality of digital signals including a first digital signal from recording and playing back means for making a digital recording and playback through a recording medium, a second switch to supply a selected signal from a plurality of analog signals including the analog signal from the D/A converter, and an analog-to-digital converter (hereinafter referred to as an A/D converter) to convert the analog signal from the second switch into a second digital signal which is adapted to be directly or selectively supplied to the recording and playing back means.
    Type: Grant
    Filed: April 5, 1988
    Date of Patent: February 20, 1990
    Assignee: Nakamichi Corporation
    Inventor: Takeshi Nakamichi
  • Patent number: 4901078
    Abstract: A high resolution analog to digital (A/D) converter amplifies and filters a magnitude difference between a pulse width modulated offset voltage and an input voltage to produce an amplified filtered difference voltage, the duty cycle of offset voltage modulation being adjusted such that the magnitude of the difference voltage is within a narrow input voltage range of a recirculating remainder A/D converter. The amplified, filtered difference voltage is converted to representative digital data by the recirculating remainder A/D converter. A microprocessor, which controls the offset voltage, combines the result with the magnitude of the offset voltage to produce a comparatively high resolution digital representation of the input voltage.
    Type: Grant
    Filed: July 29, 1988
    Date of Patent: February 13, 1990
    Assignee: John Fluke Mfg. Co., Inc.
    Inventor: Ramesh C. Goyal
  • Patent number: 4901189
    Abstract: A terminal block (20) includes a plurality of wells each having a protector 32) disposed therein and each having a bore which communicates with a U-shaped terminal (60) so that a portion of the protector extends through the bore into engagement with a bade (66) of the terminal. Tangs (68--68) of each terminal depend downwardly. Also, the terminal block includes a plurality of terminal posts (62--62) each having a spade (69) depending therefrom. A first plastic material (70) encapsulates the base and innermost portions of each U-shaped terminal and post. Individual conductors of a pair in a cable (50) extend to a depending tang of a terminal and to a tang of an associated terminal. A strap wire interconnects the other depending tang of each U-shaped terminal to a spade of an associated terminal post. A second plastic material encapsulates the wiring and the outermost portions of the U-shaped terminals and of the spades of the terminal posts.
    Type: Grant
    Filed: June 24, 1988
    Date of Patent: February 13, 1990
    Assignee: American Telephone and Telegraph Company, AT&T Technologies, Inc.
    Inventors: Glenn A. Merriman, Michael E. Szymanski
  • Patent number: 4899247
    Abstract: An auto-recloser for a power line has a high voltage closing coil (12) for closing the main contact (14) in the power line, the closing coil being energized via a non-latching switching (18) in turn controlled by a low voltage closing coil (20). A time closing pulse is applied to the low voltage coil (20) to close switch (18) for a very short time period. A coil protection (24) monitors the status of the main contants (14) and if these have not closed after a preselected time period of typically 100 ms then the protection circuit opens a normally closed switch in series with the low voltage coil (20) to prevent further closing pulses being applied in further attempts to close the main contacts (14).
    Type: Grant
    Filed: July 6, 1988
    Date of Patent: February 6, 1990
    Assignee: Brush Switchgear Limited
    Inventor: John S. Stewart
  • Patent number: 4899147
    Abstract: A data compression/decompression apparatus employs common circuitry and a single string table for compression and decompression. A throttle control is provided to prevent data under-runs and an optimizing start-up control delays the start-up of the recording device until the compression apparatus has compressed sufficient data to effeciently reduce throttling and loss of compression when the output device is started. The decompression apparatus may operate to decompress compressed data when the compressed data is read in either the same direction as it was recorded, or read in the direction reverse to that in which it was recorded. A further feature is the provision of a counter which is incremented by one after a predetermined number of string codes have been written into the string table. The output of the counter is stored in the string table with each string code and prefix code.
    Type: Grant
    Filed: June 3, 1988
    Date of Patent: February 6, 1990
    Assignee: Unisys Corporation
    Inventors: Anthony P. Schiavo, Paul H. Selby, III, Harold L. Gibson
  • Patent number: 4897650
    Abstract: An analog-to-digital converter macrocell architecture is provided with digital logic for accumulating code-density data for dynamic characterization of the converter. Each macrocell includes an A/D converter (10), a comparator (12), a bin counter (14), a clock counter (16), and a histogram counter (18). the code output of the A/D converter (10) is compared in the comparator (12) with the output of the bin counter (14) and each match increments the histogram counter (18). The histogram counter (18) accumulates code-density data for A/D converter dynamic characterization, these data being read once for every cycle of the clock counter (16).
    Type: Grant
    Filed: April 5, 1988
    Date of Patent: January 30, 1990
    Assignee: General Electric Company
    Inventors: James T. Shott, III, Edward B. Stokes
  • Patent number: 4896243
    Abstract: An efficient ESD protection circuit is provided having a resistor (18) disposed between an input pin (12) and the functioning circuitry (22) of an integrated circuit package. A primary switching device (28) is electrically connected between the input pin (12) and a reference voltage pin (14). The resistor (18) comprises an N- well (48) formed within the P- substrate (44) and an N+ diffused reion (50) formed within the N- well (48). A silicided layer (52) is formed over the N+ region (50). The primary switching device (28) is constructed to share the same PN junction (54) utilized by the resistor (18). In constructing the primary switching device (28), a P+ region (70) is formed within the N- well (48). Further, an N+ region (68) is formed within the P- substrate (44). Thus, the primary switching device (40) includes three PN junctions (72, 54, 74) which will conduct at a time prior to, or contemporaneous with, the breakdown of resistor (18).
    Type: Grant
    Filed: December 20, 1988
    Date of Patent: January 23, 1990
    Assignee: Texas Instruments Incorporated
    Inventors: Amitava Chatterjee, Charvaka Duvvury
  • Patent number: 4896024
    Abstract: An apparatus for dispensing and returning reusable articles each identifiable with its own identification code, comprising: a pair of opposing, stationary arrays of locations, each location being capable of holding a reusable article therein and having its own particular location code; a memory adapted to store details of the location codes and the article codes in memory; a data receiver for receiving informational data from a patron; a receptacle for receiving and discharging the articles; a transfer mechanism for placing an article in a location in the arrays or removing an article therefrom, the transfer mechanism being movable relative to the arrays between operative engagement with any of the locations and the receptacle; an article code sensing device adapted to sense the article code of an article carried by the transfer mechanism; and a control device having means for receiving control information and for generating output instructional information and control signals, the control device being respon
    Type: Grant
    Filed: October 19, 1987
    Date of Patent: January 23, 1990
    Assignee: Diebold, Incorporated
    Inventors: Herbert Morello, F. Michael Theriault, Michael H. Wellman
  • Patent number: 4894518
    Abstract: An electric oven such as a toaster oven according to this invention includes in addition to a heating chamber, a heater for the heating chamber and a temperature detector for measuring the temperature therein, a control device serving to automatically determine a target temperature on the basis of the initial temperature inside the heating chamber so that a desired degree of heating can be effected independently of the initial temperature inside the heating chamber by switching off the power supply when the detected temperature reaches the target temperature thus set.
    Type: Grant
    Filed: January 6, 1989
    Date of Patent: January 16, 1990
    Assignee: Sharp Kabushiki Kaisha
    Inventors: Kazuhiko Ishikawa, Yoichi Takahashi
  • Patent number: 4893213
    Abstract: The present invention pertains to a multi-stage solenoid in a housing having a first set of electrical contacts and at least a second set of electrical contacts. The solenoid also has at least two coil windings electrically distinct from each other and disposed sequentially in the housing. Additionally, the solenoid uses a timing circuit separately connected through a first set of contacts to each of the coil windings to control when they each receive electricity thereby activating the corresponding magnetically responsive element. The solenoid also uses a plunger having a flange of an electrically conducting material. The plunger is disposed in an original position in the housing in contact with one of the magnetically responsive elements.
    Type: Grant
    Filed: June 17, 1988
    Date of Patent: January 9, 1990
    Assignee: R.P.M. Industries
    Inventor: John K. Apostolides
  • Patent number: 4893212
    Abstract: A power integrated-circuit device is protected against load voltage surges. This is done by providing an alternate current-carrying path that is activated only in response to the occurrence of such surges. This alternate path is independent of and separate from the connection that extends between the device and its power supply source. In addition, circuitry is connected to the device to limit the portion of the surge voltage that can appear across critical elements of the device.
    Type: Grant
    Filed: December 20, 1988
    Date of Patent: January 9, 1990
    Assignee: North American Philips Corp.
    Inventors: Stephen L. Wong, Satyendranath Mukherjee
  • Patent number: 4890187
    Abstract: To protect integrated circuits as efficiently as possible against electrostatic discharges, by putting a diode in avalanche mode without untimely triggering of this avalance mode by overvoltages of non-electrostatic origin, the following solution is proposed: through an insulated gate surrounding the cathode of the diode, the threshold for transition into avalanche mode of the diode is modified according to the slope of the overvoltages appearing at the terminal to be protected. The gate is connected to the terminal by an integrating circuit in such a way that the overvoltages are applied to the gate with a certain delay, inducing a potential difference between the cathode and the gate which is all the greater as the front of the overvoltage is steep. The avalanche triggering threshold is higher in the latter case than in the former one, and it is thus distinguish between overvoltages of diverse origins.
    Type: Grant
    Filed: October 28, 1988
    Date of Patent: December 26, 1989
    Assignee: SGS-Thomson Microelectronics, SA
    Inventors: Francois Tailliet, Jacek Kowalski
  • Patent number: 4888589
    Abstract: A digital-to-analog converter (DAC) ladder segment is disclosed in which diode networks are introduced into the ladder step circuits. Each diode network includes a control diode which controls the flow of current through the network in accordance with a signal from an associated actuating circuit, which in turn is controlled by an input digital signal. In one embodiment, the control diodes are connected in series with resistors, with the diodes and resistors scaled so that their respective bit circuits conduct desired current levels. In another embodiment, the control diodes have equal scalings and are connected in series with respective resistors and second diodes which are called so that their step circuits conduct the desired currents. In a third embodiment, current sources are provided which supply currents to the second diodes in amounts that permit the second diode and the resistors for the various step circuits to have substantially equal scalings.
    Type: Grant
    Filed: June 9, 1988
    Date of Patent: December 19, 1989
    Assignee: Precision Monolithics, Inc.
    Inventor: Derek F. Bowers
  • Patent number: 4887183
    Abstract: A thermal protection device for overvoltage suppressor which includes spaced contacts 6 mounted in overvoltage suppressor magazines 11 of communication systems. A bow-type spring 3 and a melt element 2 l are arranged with the overvoltage suppressor which is mounted in a chamber of a case body or housing 13. The melt element is pierced by at least one arm of the bow-type spring when an overvoltage occurs for short-circuiting the two contacts of the overvoltage suppressor. A thermal protection device with simple components prevents creepage currents between the bow-type spring and the contacts of the overvoltage suppressor 6, a chamber for the overvoltage suppressor is adjacent and abutting to a separate chamber formed in the case body for accommodating a bow-type spring. Between the two chambers there is a separating wall comprising a thermoplastic melt element.
    Type: Grant
    Filed: October 13, 1988
    Date of Patent: December 12, 1989
    Assignee: Krone AG
    Inventors: Lutz Biederstedt, Manfred Muller
  • Patent number: 4885584
    Abstract: In the serializer for converting parallel data into serial data, where the parallel data comprises normal characters all of the same length and a last character of a different length, the characters are each tagged by an extra bit as it enters a FIFO. This tag bit indicates the length of the character and is shifted along with the character as the character is shifted through the FIFO. The normal character length and the length of the last character are stored. As a character emerges from the FIFO, its tag bit identifies it as a normal character or as the last character. Such tag bit is used to select the correct character length in a counter. The character is loaded in a shifter which is controlled by the counter. Therefore, the shifter is controlled by the counter to shift the correct number of times in order to shift the character into a serial bit stream.
    Type: Grant
    Filed: April 7, 1988
    Date of Patent: December 5, 1989
    Assignee: Zilog, Inc.
    Inventor: Monte J. Dalrymple
  • Patent number: 4885657
    Abstract: In a thyristor with turn-off facility (AT) and overvoltage protection, the voltage limitation is achieved by a parallel-connected controllable resistor, in particular in the form of a J-FET (JF) which is driven by an overvoltage sensor (OS).The separation of sensor function and bypass function produce advantages for a simple and compact construction.
    Type: Grant
    Filed: December 22, 1988
    Date of Patent: December 5, 1989
    Assignee: BBC Brown Boveri AG
    Inventor: Horst Gruning
  • Patent number: 4884033
    Abstract: A test module incorporating a unique diagnostic circuit for monitoring the magnitude of electrical parameters existing between an electrical driver such as the electronic control module (ECM) of an automotive vehicle and an electrical load in the vehicle's electrical system. The circuit employs a visual indicator connected to a point adjacent the driver to provide a visual signal when the voltage at the point of connection lies within a predetermined range with respect to electrical ground. An additional visual indicator, separate from the first, is connected to a point adjacent to the electrical load, and provides a visual signal when the voltage at its point of connection lies within a predetermined range with respect to electrical ground. A third visual indicator is connected between the driver and load, and provides a visual signal in response to current flowing between the driver and load.
    Type: Grant
    Filed: June 6, 1988
    Date of Patent: November 28, 1989
    Inventor: Noel P. McConchie Sr.