Abstract: Approaches based on differential hardmasks for modulation of electrobucket sensitivity for semiconductor structure fabrication, and the resulting structures, are described. In an example, a method of fabricating an interconnect structure for an integrated circuit includes forming a hardmask layer above an inter-layer dielectric (ILD) layer formed above a substrate. A plurality of dielectric spacers is formed on the hardmask layer. The hardmask layer is patterned to form a plurality of first hardmask portions. A plurality of second hardmask portions is formed alternating with the first hardmask portions. A plurality of electrobuckets is formed on the alternating first and second hardmask portions and in openings between the plurality of dielectric spacers. Select ones of the plurality of electrobuckets are exposed to a lithographic exposure and removed to define a set of via locations.

Abstract: The magnetoresistive stack or structure of a magnetoresistive device includes one or more electrodes or electrically conductive lines, a magnetically fixed region, a magnetically free region disposed between the electrodes or electrically conductive lines, and a dielectric layer disposed between the free and fixed regions. The magnetoresistive device may further include a spin-Hall (SH) material proximate to at least a portion of the free region, and one or more insertion layers comprising antiferromagnetic material.

Abstract: A method for manufacturing a semiconductor device includes forming a first vertical transistor on a semiconductor substrate, and forming a second vertical transistor stacked on the first vertical transistor. In the method, an isolation layer is formed between the first and second vertical transistors. The isolation layer includes a rare earth oxide.

Abstract: A phase change memory cell for a semiconductor device that includes a heater element on a first conductive layer with a spacer surrounding sides of the heater element. The phase change memory cell includes a first dielectric layer on the conductive layer and on a bottom portion of the spacer surrounding the heater element and a second dielectric layer on the first dielectric layer surrounding a top portion of the heater element. The phase change memory cell includes a phase change material on a top surface of the heater element and on the second dielectric material.

Abstract: A memory device including a rectangular shaped via for at least one Vss node connection. In some embodiments, the rectangular shaped via has a length/width of greater than 1.5. The rectangular shaped via may be disposed on the Via0 and/or Via1 layer interfacing a first metal layer (e.g., M1). The memory cell may also include circular/square shaped vias having a length/width of between approximately 0.8 and 1.2. The circular/square shaped vias may be coplanar with the rectangular shaped vias.

Abstract: [Object] To provide a semiconductor device capable of improving a discharge starting voltage when measuring electric characteristics, and widening a pad area of a surface electrode or increasing the number of semiconductor devices (number of chips) to be obtained from one wafer, and a method for manufacturing the same. [Solution Means] A semiconductor device 1 includes an n-type SiC layer 2 having a first surface 2A, a second surface 2B, and end faces 2C, a p-type voltage relaxing layer 7 formed in the SiC layer 2 so as to be exposed to the end portion of the first surface 2A of the SiC layer 2, an insulating layer 8 formed on the SiC layer 2 so as to cover the voltage relaxing layer 7, and an anode electrode 9 that is connected to the first surface 2A of the SiC layer 2 through the insulating layer 8 and has a pad area 95 selectively exposed.

Abstract: A semiconductor structure includes a substrate; a resistance variable layer disposed over the substrate; a gate structure disposed over the resistance variable layer; a dielectric layer disposed over the resistance variable layer and surrounding the gate structure; a first contact plug disposed over the resistance variable layer and extending through the dielectric layer; and a second contact plug disposed over the resistance variable layer and opposite to the first contact plug and extending through the dielectric layer, wherein the resistance variable layer is semiconductive and ferroelectric.

Abstract: An electronic device including: a semiconductor device including plural terminals input with voltages having a same potential; and a wiring board including a mounting region at which the semiconductor device is mounted, wherein the wiring board includes a board wiring line formed on the wiring board from a connection portion at which one terminal of the plural terminals is connected, via an inside of the mounting region, to a connection portion at which another terminal of the plural terminals is connected.

Abstract: Provided is a nanorod light-emitting device including a first semiconductor layer doped with a first conductive type impurity, an emission layer disposed above the first semiconductor layer, a second semiconductor layer disposed above the emission layer and doped with a second conductive type impurity that is electrically opposite to the first conductive type impurity, a conductive layer disposed between at least one of a center portion of a lower surface of the emission layer and the first semiconductor layer and a center portion of an upper surface of the emission layer and the second semiconductor layer, and a current blocking layer surrounding a sidewall of the conductive layer.

Abstract: Provided are MIM capacitor and semiconductor structure including MIM capacitor. The MIM capacitor includes a dielectric structure, a bottom electrode on the dielectric structure, a first insulating layer covering the bottom electrode and the dielectric structure, a middle electrode stacked on the bottom electrode, a spacer, a second insulating layer and a top electrode. The middle electrode is separate from the bottom electrode by the first insulating layer therebetween. A bottommost surface of the middle electrode is lower than a top surface of the bottom electrode and higher than a bottom surface of the bottom electrode. The spacer is disposed on the first insulating layer and laterally aside and covers a sidewall of the middle electrode. The second insulating layer covers the middle electrode and the spacer. The top electrode is stacked on the middle electrode and separate from the middle electrode by the second insulating layer therebetween.

Abstract: A magnetic field sensor may include a semiconductor structure having a planar surface, and first, second, and third sensing devices. The semiconductor structure may include a semiconductor member having a two-dimensional electron gas therein, and an insulator member disposed on the semiconductor member. The first sensing device may be configured to sense magnetic field along a first axis parallel to the planar surface. The second sensing device may be configured to sense magnetic field along a second axis parallel to the planar surface, and orthogonal to the first axis. The third sensing device may be configured to sense a magnetic field along a third axis normal to the planar surface. Each of the first, second, and third sensing devices may be formed in the semiconductor structure and may include electrodes that extend from the insulator member to the two-dimensional electron gas.

Abstract: A wiring substrate device includes a wiring substrate, a plurality of terminals each of which is provided upright on the wiring substrate and has a lower end, an upper end and a narrowed part between the lower end and the upper end, and a plurality of solders each of which has a melting point lower than the terminals and covers a surface of the corresponding terminal.

Abstract: A semiconductor device includes a storage element layer and a selector. The selector is electrically coupled to the storage element layer, and includes a first insulating layer, a second insulating layer, a third insulating layer, a first conductive layer and a second conductive layer. The first insulating layer, the second insulating layer and the third insulating layer are stacked up in sequence, wherein the second insulating layer is sandwiched in between the first insulating layer and the third insulating layer, and the first insulating layer and the third insulating layer include materials with higher band gap as compared with a material of the second insulating layer. The first conductive layer is connected to the first insulting layer, and the second conductive layer is connected to the third insulating layer.

Abstract: A semiconductor memory includes a stack section comprising a first area including a plurality of first conductors and a plurality of first insulators alternately stacked in a first direction and memory cells, and a second area including respective end portions of the plurality of stacked first conductors and the plurality of stacked first insulators, a plurality of contact plugs respectively reaching the plurality of first conductors in the second area, first and second supporting portions configured respectively to pass through the stack section in the first direction and arranged in a second direction, which crosses the first direction, in the second area, and a layer between respective adjacent first insulators, among the plurality of first insulators that are stacked, between the first supporting portion and the second supporting portion, wherein the layer is made of a material that is different from that of the first conductors.

Abstract: A Micro-LED array device based on III-nitride semiconductors and a method for fabricating the same are provided. The Micro-LED array device includes arrayed sector mesa structures that are formed by etching to penetrate through a p-type GaN layer and a quantum-well active layer and deep into an n-type GaN layer, a p-type electrode array deposited by evaporation on the p-type GaN layer of sector arrays, and an n-type electrode array deposited by evaporation on the n-type GaN layer. The n-type electrode array forms blocking walls to isolate the sector mesas from one another. The blocking walls, and each of the blocking walls and the annular structure surrounding the sector mesa are connected to each other.

Abstract: An aspect of the invention relates to an elementary cell that includes a breakdown layer made of dielectric having a thickness that depends on a breakdown voltage, a device and a non-volatile resistive memory mounted in series, the device including an upper selector electrode, a lower selector electrode, a layer made in a first active material, referred to as active selector layer, the device being intended to form a volatile selector; the memory including an upper memory electrode, a lower memory electrode, a layer made in at least one second active material, referred to as active memory layer.

Abstract: A phase-change memory (PCM) device includes a first electrode, a second electrode, a memory layer, and a heater. The memory layer includes a phase-change material and is electrically coupled between the first electrode and the second electrode. The heater is arranged near the memory layer and is configured to heat a programming region of the memory layer in response to an electric current that passes through the heater. The heater is coupled to a power source via an electric current path that does not pass through the memory layer.

Abstract: In some embodiments, a semiconductor structure includes: a first epitaxial oxide semiconductor layer; a metal layer; and a contact layer adjacent to the metal layer, and between the first epitaxial oxide semiconductor layer and the metal layer. The contact layer can include an epitaxial oxide semiconductor material. The contact layer can also include a region comprising a gradient in a composition of the epitaxial oxide semiconductor material adjacent to the metal layer, or a gradient in a strain of the epitaxial oxide semiconductor material over a region adjacent to the metal layer.

Abstract: A memory device enabling a reduced minimal conductance state may be provided. The device comprises a first electrode, a second electrode and phase-change material between the first electrode and the second electrode, wherein the phase-change material enables a plurality of conductivity states depending on the ratio between a crystalline and an amorphous phase of the phase-change material. The memory device comprises additionally a projection layer portion in a region between the first electrode and the second electrode. Thereby, an area directly covered by the phase-change material in the amorphous phase in a reset state of the memory device is larger than an area of the projection layer portion oriented to the phase-change material, such that a discontinuity in the conductance states of the memory device is created and a reduced minimal conductance state of the memory device in a reset state is enabled.

Abstract: A transistor with stable electrical characteristics. A semiconductor device includes a first insulator over a substrate, a second insulator over the first insulator, an oxide semiconductor in contact with at least part of a top surface of the second insulator, a third insulator in contact with at least part of a top surface of the oxide semiconductor, a first conductor and a second conductor electrically connected to the oxide semiconductor, a fourth insulator over the third insulator, a third conductor which is over the fourth insulator and at least part of which is between the first conductor and the second conductor, and a fifth insulator over the third conductor. The first insulator contains a halogen element.