Patents Examined by Hajar Kolahdouzan
  • Patent number: 10854576
    Abstract: A semiconductor device includes a wiring substrate having a first surface, a stacked body on the first surface, the stacked body comprising a first chip, a second chip having a through via and positioned between the first chip and the first surface, and a third chip, a first resin contacting the first surface and the third chip, and a second resin sealing the stacked body. The first and second resins are made of different materials.
    Type: Grant
    Filed: September 3, 2017
    Date of Patent: December 1, 2020
    Assignee: TOSHIBA MEMORY CORPORATION
    Inventors: Yuji Karakane, Masatoshi Fukuda, Soichi Homma, Masayuki Miura, Naoyuki Komuta, Yuka Akahane, Yukifumi Oyama
  • Patent number: 10847418
    Abstract: A method for forming a semiconductor device is provided. The method includes forming a first dielectric layer over a semiconductor substrate and forming a first conductive feature extending into the first dielectric layer. The first conductive feature has a planar top surface. The method also includes forming a second dielectric layer over the first conductive feature. The method further includes forming a hole in the second dielectric layer to expose the planar top surface of the first conductive feature. In addition, the method includes partially removing the first conductive feature from the planar top surface of the first conductive feature to form a curved surface of the first conductive feature. The method further includes forming a second conductive feature to fill the hole after the curved surface of the first conductive feature is formed.
    Type: Grant
    Filed: September 27, 2019
    Date of Patent: November 24, 2020
    Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Tai-Yen Peng, Chia-Tien Wu, Jye-Yen Cheng
  • Patent number: 10825894
    Abstract: Provided are MIM capacitor and method of manufacturing the same. The MIM capacitor includes a first electrode, a second electrode, a third electrode, a first insulating layer, a second insulating layer, and a first spacer. The first electrode and the third electrode are electrically connected to each other. The first insulating layer is between the first electrode and the second electrode. The second insulating layer is between the second electrode and the third electrode. The first spacer is located between a sidewall of the first electrode and the first insulating layer.
    Type: Grant
    Filed: March 29, 2018
    Date of Patent: November 3, 2020
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Tung-Jiun Wu, Shun-Yi Lee
  • Patent number: 10804378
    Abstract: A method is performed to a structure that includes a substrate with first and second regions for logic and RF devices respectively, first fin and first gate structure over the first region, second fin and second gate structure over the second region, and gate spacers over sidewalls of the gate structures. The method includes performing a first etching to the first fin to form a first recess; and performing a second etching to the second fin to form a second recess. The first and second etching are tuned to differ in at least one parameter such that the first recess is shallower than the second recess and a first distance between the first recess and the first gate structure along the first fin lengthwise is smaller than a second distance between the second recess and the second gate structure along the second fin lengthwise.
    Type: Grant
    Filed: March 23, 2018
    Date of Patent: October 13, 2020
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
    Inventors: Fu-Tsun Tsai, Tong Jun Huang, I-Chih Chen, Chi-Cherng Jeng
  • Patent number: 10804354
    Abstract: A radio frequency resistor element comprises a resistive polysilicon trace, an isolation component and a semiconductor substrate. The resistive polysilicon trace is located above the isolation component. The isolation component is laterally at least partially surrounded by a modified semiconductor region located above the semiconductor substrate and having a higher charge carrier recombination rate than the semiconductor substrate.
    Type: Grant
    Filed: March 23, 2018
    Date of Patent: October 13, 2020
    Assignee: INFINEON TECHNOLOGIES AG
    Inventors: Hans Taddiken, Martin Bartels, Andrea Cattaneo, Henning Feick, Christian Kuehn, Anton Steltenpohl
  • Patent number: 10797103
    Abstract: A method for producing a bolometric detector comprising producing a stack, on an interconnect level of a read-out circuit, comprising a sacrificial layer positioned between a carrier layer and an etch stop layer, the sacrificial layer comprising a mineral material; producing a conducting via passing through the stack such that it is in contact with a conducting portion of said interconnect level; depositing a conducting layer onto the carrier layer and the via; etching the conducting layer and the carrier layer, forming a bolometer membrane electrically connected to the via by a remaining portion of the conducting layer that covers an upper part of the via; and elimination of the sacrificial layer by selective chemical etching, and such that the membrane is suspended by the via.
    Type: Grant
    Filed: May 2, 2018
    Date of Patent: October 6, 2020
    Assignee: COMMISSARIAT A L'ENERGIE ATOMIQUE ET AUX ENERGIES ALTERNATIVES
    Inventors: Patrick Leduc, Sebastien Cortial, Stephane Pocas, Jean-Jacques Yon
  • Patent number: 10761630
    Abstract: A display substrate, a display device, and a touch panel, the display substrate including a base substrate; and an electrode on the base substrate, the electrode including a first light transmitting layer, wherein the first light transmitting layer has a work function ranging from about 4.75 eV to about 4.9 eV, the first light transmitting layer includes a first transparent conductive oxide (TCO) layer and a first metal element doped in the first transparent conductive oxide layer, the first metal element being a group 2 metal element, the first metal element is included in the first light transmitting layer in an amount of about 0.01 atomic percent (atomic %) to about 5.00 atomic %, based on a total number of atoms in the first light transmitting layer.
    Type: Grant
    Filed: July 6, 2017
    Date of Patent: September 1, 2020
    Assignee: SAMSUNG DISPLAY CO., LTD.
    Inventors: Hyuneok Shin, Dokeun Song, Sangwon Shin, Dongmin Lee, Hyunju Kang, Chanwoo Yang, Juhyun Lee, Gwangmin Cha
  • Patent number: 10752993
    Abstract: Provided is a substrate processing apparatus and substrate processing method for depositing a thin film on a substrate. The substrate processing apparatus may include a chamber, a susceptor rotatably mounted in the chamber, at least one satellite mounted on the susceptor, configured to place a substrate thereon, and capable of being floated and rotating due to pressure of a gas supplied through the susceptor, to rotate the substrate, and of revolving due to rotation of the susceptor, and a cart lifting module including a cart mounted on the susceptor around the satellite and supporting an edge of the substrate to take over the substrate and place the substrate on the satellite, and a cart lifting device capable of lifting and lowering the cart.
    Type: Grant
    Filed: October 17, 2017
    Date of Patent: August 25, 2020
    Assignee: WONIK IPS CO., LTD.
    Inventors: Wook Sang Jang, Sang Jun Park, Ho Young Lee
  • Patent number: 10741650
    Abstract: According to one embodiment, a semiconductor device includes a semiconductor element having a substrate with at least two bending portions formed on a first side surface thereof. The two bending portions are displaced from each other in a first direction that is perpendicular to the first side surface of the substrate and parallel to a front surface of the substrate and in a second direction parallel to the front surface of the substrate and perpendicular to a top surface of the substrate. A rearmost portion of the first side surface is substantially perpendicular to the front surface.
    Type: Grant
    Filed: September 4, 2017
    Date of Patent: August 11, 2020
    Assignee: TOSHIBA MEMORY CORPORATION
    Inventors: Tsutomu Fujita, Takanobu Ono, Makoto Minaminaka
  • Patent number: 10741607
    Abstract: A method of manufacturing an image sensing apparatus includes: forming a first substrate structure including a first region of a pixel region, the first substrate structure having a first surface and a second surface; forming a second substrate structure including a circuit region for driving the pixel region, the second substrate structure having a third surface and a fourth surface; bonding the first substrate structure to the second substrate structure, such that the first surface is connected to the third surface; forming a second region of the pixel region on the second surface; forming a first connection via, the first connection via extending from the second surface to pass through the first substrate structure; mounting semiconductor chips on the fourth surface, using a conductive bump; and separating a stack structure of the first substrate structure, the second substrate structure, and the semiconductor chips into unit image sensing apparatuses.
    Type: Grant
    Filed: May 2, 2018
    Date of Patent: August 11, 2020
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Sung Hyun Yoon, Doo Won Kwon, Kwan Sik Kim, In Gyu Baek, Tae Young Song
  • Patent number: 10727152
    Abstract: A semiconductor apparatus includes: a radiator plate; a resin insulating layer provided on the radiator plate; a resin block made of resin and armularly disposed to cover an end part of the radiator plate and an end part of the resin insulating layer; a case disposed to cover the resin block; and a sealing material filled in an inside of the case.
    Type: Grant
    Filed: March 29, 2018
    Date of Patent: July 28, 2020
    Assignee: Mitsubishi Electric Corporation
    Inventor: Hiroki Tanaka
  • Patent number: 10727082
    Abstract: A semiconductor device includes a semiconductor die. A dielectric material surrounds the semiconductor die to form an integrated semiconductor package. There is a contact coupling to the integrated semiconductor package and configured as a ground terminal for the semiconductor package. The semiconductor device further has an EMI (Electric Magnetic Interference) shield substantially enclosing the integrated semiconductor package, wherein the EMI shield is coupled with the contact through a path disposed in the integrated semiconductor package.
    Type: Grant
    Filed: August 28, 2015
    Date of Patent: July 28, 2020
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY LTD.
    Inventors: Shou Zen Chang, Chun-Lin Lu, Kai-Chiang Wu, Ching-Feng Yang, Vincent Chen, Chuei-Tang Wang, Yen-Ping Wang, Hsien-Wei Chen, Wei-Ting Lin
  • Patent number: 10714375
    Abstract: A semiconductor device is provided in which a zener diode having a desired breakdown voltage and a capacitor in which voltage dependence of capacitance is reduced are mounted together, and various circuits are realized. The semiconductor device includes: a semiconductor layer; a first conductivity type well that is arranged in a first region of the semiconductor layer; a first conductivity type first impurity diffusion region that is arranged in the well; a first conductivity type second impurity diffusion region that is arranged in a second region of the semiconductor layer; an insulating film that is arranged on the second impurity diffusion region; an electrode that is arranged on the insulating film; and a second conductivity type third impurity diffusion region that is arranged at least on the first impurity diffusion region.
    Type: Grant
    Filed: November 30, 2016
    Date of Patent: July 14, 2020
    Assignee: SEIKO EPSON CORPORATION
    Inventors: Kazunobu Kuwazawa, Shigeyuki Sakuma, Hiroaki Nitta, Mitsuo Sekisawa, Takehiro Endo
  • Patent number: 10692931
    Abstract: An electronic device includes a semiconductor memory. The semiconductor memory includes stack structures, a gap-fill layer filling spaces between the stack structures, and nanopores located in the gap-fill layer. Each of the stack structures includes a memory pattern. The nanopores are distributed in a portion of the gap-fill layer that is located at a level corresponding to where the memory pattern is located in each of the stack structures.
    Type: Grant
    Filed: August 22, 2018
    Date of Patent: June 23, 2020
    Assignee: SK hynix Inc.
    Inventor: Hyung Suk Lee
  • Patent number: 10629643
    Abstract: An integrated circuit (IC) device includes a first substrate and a first structure on a front surface of the first substrate. The first structure includes a first interlayer insulating layer structure including a plurality of first conductive pad layers spaced apart from one another at different levels of the first interlayer insulating layer structure. The IC device includes a second substrate on the first substrate and a second structure on a front surface of the second substrate, which faces the front surface of the first substrate. The second structure includes a second interlayer insulating layer structure bonded to the first interlayer insulating layer structure. A through-silicon via (TSV) structure penetrates the second substrate and the second interlayer insulating layer structure. The TSV structure is in contact with at least two first conductive pad layers of the plurality of first conductive pad layers located at different levels.
    Type: Grant
    Filed: August 3, 2016
    Date of Patent: April 21, 2020
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Sun-hyun Kim, Sang-il Jung, Byung-jun Park
  • Patent number: 10622368
    Abstract: Azimuthally-split metal-semiconductor alloy floating gate electrodes can be formed by providing an alternating stack of insulating layers and spacer material layers, forming a dielectric separator structure extending through the alternating stack, and forming memory openings that divides the dielectric separator structure into a plurality of dielectric separator structures. The spacer material layers are formed as, or are replaced with, electrically conductive layers, which are laterally recessed selective to the insulating layers and the plurality of dielectric separator structures to form a pair of lateral cavities at each level of the electrically conductive layers in each memory opening. After formation of a blocking dielectric layer, a pair of physically disjoined metal-semiconductor alloy portions are formed in each pair of lateral cavities as floating gate electrodes. A tunneling dielectric layer and a semiconductor channel layer is subsequently formed in each memory opening.
    Type: Grant
    Filed: August 3, 2016
    Date of Patent: April 14, 2020
    Assignee: SANDISK TECHNOLOGIES LLC
    Inventors: Senaka Kanakamedala, Raghuveer S. Makala, Rahul Sharangpani, Somesh Peri, Yao-Sheng Lee, James Kai
  • Patent number: 10615042
    Abstract: A method of manufacturing a semiconductor apparatus comprises forming a first photoresist on each of a first portion and a second portion of a member, exposing the first photoresist on the first portion using a first photomask, exposing the first photoresist on the second portion using a second photomask, forming a first resist pattern by developing the first photoresist on the first portion and the second portion, etching the first portion and the second portion using the first resist pattern as a mask, forming a second photoresist on a third portion of the member, exposing the second photoresist on the third portion using a third photomask, forming a second resist pattern by developing the second photoresist on the third portion, and etching the third portion using the second resist pattern as a mask.
    Type: Grant
    Filed: May 2, 2018
    Date of Patent: April 7, 2020
    Assignee: CANON KABUSHIKI KAISHA
    Inventor: Nobuyuki Endo
  • Patent number: 10608078
    Abstract: A bonded substrate for epitaxial growth and a method for forming the same are disclosed. The method includes steps of providing a first substrate, which has a first dopant concentration; providing a second substrate, which has a second dopant concentration, wherein the second dopant concentration is lower than the first dopant concentration; directly bonding a first surface of the first substrate with a second surface of the second substrate to form a bonded substrate; annealing the bonded substrate to form a high impedance layer in the bonded substrate; and removing part of the second substrate to expose the high impedance layer depending on the requirements whereby, the bonded substrate formed by the method could have a heavily doped substrate which includes a stronger strength and the impedance layer formed thereon, which could effectively increase the substrate strength, reduce the leakage current, and sustains a higher breakdown voltage.
    Type: Grant
    Filed: March 23, 2018
    Date of Patent: March 31, 2020
    Assignee: GLOBALWAFERS CO., LTD.
    Inventors: Chun-I Fan, Chih-Yuan Chuang, Man-Hsuan Lin, Wen-Ching Hsu
  • Patent number: 10574209
    Abstract: A semiconductor device includes a substrate having a front surface and a back surface, a subassembly on the front surface of the substrate including first and second metal layers insulated from each other, a cap assembly including a metal connection member, and first and second through holes penetrating through the substrate and filled with metals. The metal filled in the first through hole is electrically connected to the first metal layer, and the metal filled in the second through hole is electrically connected to the second metal layer. The semiconductor device also includes a metal connection pad on the substrate that entirely surrounds the subassembly and is aligned with the metal connection member. The interface between the cap assembly and the subassembly is free of through holes to prevent a resistance change and shield the subassembly from interference.
    Type: Grant
    Filed: October 23, 2015
    Date of Patent: February 25, 2020
    Assignee: SEMICONDUCTOR MANUFACTURING INTERNATIONAL (SHANGHAI) CORPORATION
    Inventor: Liang Liang Guo
  • Patent number: 10553765
    Abstract: A method for manufacturing a light emitting device includes: providing a substrate; placing a light emitting element on a top surface of the substrate; arranging on the top surface of the substrate a translucent frame body that is spaced apart from the light emitting element and that surrounds the light emitting element so that a top surface of the translucent frame body is at a position higher than a top surface of the light emitting element; arranging a wavelength conversion member in a region surrounded by the translucent frame body so as to cover the top surface and a side surface of the light emitting element and to be in contact with an inside surface of the frame body; and forming a translucent member that covers the substrate, the translucent frame body, and the wavelength conversion member.
    Type: Grant
    Filed: October 17, 2017
    Date of Patent: February 4, 2020
    Assignee: NICHIA CORPORATION
    Inventors: Toru Hashimoto, Takahiro Amo